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/linux/Documentation/filesystems/ext4/
H A Dblocks.rst7 sectors between 1KiB and 64KiB, and the number of sectors must be an
10 4KiB. You may experience mounting problems if block size is greater than
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
20 :widths: 1 1 1 1 1
21 :header-rows: 1
24 - 1KiB
25 - 2KiB
26 - 4KiB
27 - 64KiB
66 - 1,074,791,436
[all …]
/linux/Documentation/networking/
H A Dsmc-sysctl.rst18 the under device in 1 single sending. If set to 0, the SMC auto corking
34 - 1 - Use virtually contiguous buffers
48 The minimum value is 16KiB and there is no hard limit for max value, but
49 only allowed 512KiB for SMC-R and 1MiB for SMC-D.
51 Default: 64KiB
56 The minimum value is 16KiB and there is no hard limit for max value, but
57 only allowed 512KiB for SMC-R and 1MiB for SMC-D.
59 Default: 64KiB
64 of RDMA devices exist in the system. The acceptable value ranges from 1 to 2. Only
65 for SMC-R v2.1 and later.
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi31 <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
38 #address-cells = <1>;
43 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
64 cpu1: cpu@1 {
67 reg = <1>;
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
[all …]
H A Dbcm2836.dtsi32 <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
39 #address-cells = <1>;
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
65 v7_cpu1: cpu@1 {
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
[all …]
H A Dbcm2835.dtsi9 #address-cells = <1>;
29 d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set
32 i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set
/linux/Documentation/arch/arm/
H A Dtcm.rst8 This is usually just a few (4-64) KiB of RAM inside the ARM
15 The size of DTCM or ITCM is minimum 4KiB so the typical
16 minimum configuration is 4KiB ITCM and 4KiB DTCM.
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
39 implementation will map the TCM 1 to 1 from physical to virtual
42 on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM.
45 TCMs in two separate banks, so for example an 8KiB ITCM is divided
46 into two 4KiB banks with its own control registers. The idea is to
153 tcmem[1] = 0x2BADBABEU;
/linux/Documentation/admin-guide/device-mapper/
H A Ddm-ebs.rst30 1, 2, 4, 8 sectors of 512 bytes supported.
36 2^N supported, e.g. 8 = emulate 8 sectors of 512 bytes = 4KiB.
42 Emulate 1 sector = 512 bytes logical block size on /dev/sda starting at
45 ebs /dev/sda 1024 1
47 Emulate 2 sector = 1KiB logical block size on /dev/sda starting at
48 offset 128 sectors, enforce 2KiB underlying device block size.
49 This presumes 2KiB logical blocksize on /dev/sda or less to work:
/linux/tools/perf/arch/x86/util/
H A Dintel-bts.c28 #define KiB(x) ((x) * 1024) macro
30 #define KiB_MASK(x) (KiB(x) - 1)
31 #define MiB_MASK(x) (MiB(x) - 1)
114 bool privileged = perf_event_paranoid_check(-1); in intel_bts_recording_options()
131 evsel->core.attr.sample_period = 1; in intel_bts_recording_options()
157 opts->auxtrace_mmap_pages = KiB(128) / page_size; in intel_bts_recording_options()
159 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
163 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
194 opts->auxtrace_mmap_pages = KiB(128) / page_size; in intel_bts_recording_options()
196 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
[all …]
/linux/drivers/mtd/tests/
H A Dspeedtest.c200 if (mtd->writesize == 1) { in mtd_speedtest_init()
243 /* Write all eraseblocks, 1 eraseblock at a time */ in mtd_speedtest_init()
259 pr_info("eraseblock write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
261 /* Read all eraseblocks, 1 eraseblock at a time */ in mtd_speedtest_init()
277 pr_info("eraseblock read speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
283 /* Write all eraseblocks, 1 page at a time */ in mtd_speedtest_init()
299 pr_info("page write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
301 /* Read all eraseblocks, 1 page at a time */ in mtd_speedtest_init()
317 pr_info("page read speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
339 pr_info("2 page write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_mmu.h32 * device page sizes are: 4KiB, 16KiB, 64KiB, 256KiB, 1MiB and 2MiB.
89 #define PVR_PAGE_TABLE_ADDR_MASK (PVR_PAGE_TABLE_ADDR_SPACE_SIZE - 1)
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-rango.dts25 wan_white@1 {
86 #address-cells = <1>;
87 #size-cells = <1>;
97 reg = <0x200000 0x20000>; /* 128KiB */
102 reg = <0x220000 0x40000>; /* 256KiB */
107 reg = <0x7e0000 0x40000>; /* 256KiB */
113 reg = <0x820000 0x1e0000>; /* 1920KiB */
163 no-1-8-v;
/linux/tools/perf/arch/arm64/util/
H A Darm-spe.c32 #define KiB(x) ((x) * 1024) macro
128 if (perf_pmu__scan_file(pmu, "caps/min_interval", "%lu", &val) != 1) in arm_spe_save_cpu_header()
132 if (perf_pmu__scan_file(pmu, "caps/event_filter", "%lx", &val) != 1) in arm_spe_save_cpu_header()
194 * snapshot size is specified, then the default is 4MiB for privileged users, 128KiB for in arm_spe_snapshot_resolve_auxtrace_defaults()
197 * The default auxtrace mmap size is 4MiB/page_size for privileged users, 128KiB for in arm_spe_snapshot_resolve_auxtrace_defaults()
199 * will be reduced from the default 512KiB/page_size to 256KiB/page_size, otherwise the in arm_spe_snapshot_resolve_auxtrace_defaults()
210 opts->auxtrace_mmap_pages = KiB(128) / page_size; in arm_spe_snapshot_resolve_auxtrace_defaults()
212 opts->mmap_pages = KiB(256) / page_size; in arm_spe_snapshot_resolve_auxtrace_defaults()
215 opts->mmap_pages = KiB(256) / page_size; in arm_spe_snapshot_resolve_auxtrace_defaults()
249 &sample_period) != 1) { in arm_spe_pmu__sample_period()
[all …]
H A Dhisi-ptt.c27 #define KiB(x) ((x) * 1024) macro
66 bool privileged = perf_event_paranoid_check(-1); in hisi_ptt_set_auxtrace_mmap_page()
75 opts->auxtrace_mmap_pages = KiB(128) / page_size; in hisi_ptt_set_auxtrace_mmap_page()
77 opts->mmap_pages = KiB(256) / page_size; in hisi_ptt_set_auxtrace_mmap_page()
84 size_t min_sz = KiB(8); in hisi_ptt_set_auxtrace_mmap_page()
115 evsel->core.attr.sample_period = 1; in hisi_ptt_recording_options()
141 tracking_evsel->core.attr.sample_period = 1; in hisi_ptt_recording_options()
/linux/drivers/mtd/nand/onenand/
H A DKconfig16 from 1 to 0. There is a rare possibility that even though the
49 Also, 1st Block of NAND Flash Array can be used as OTP.
63 of 4KiB. Plane1 has only even blocks such as block0, block2, block4
65 So MTD regards it as 4KiB page size and 256KiB block size
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi34 d-cache-size = <0x8000>; /* 32 KiB */
37 i-cache-size = <0x8000>; /* 32 KiB */
43 cpu@1 {
48 d-cache-size = <0x8000>; /* 32 KiB */
51 i-cache-size = <0x8000>; /* 32 KiB */
62 d-cache-size = <0x8000>; /* 32 KiB */
65 i-cache-size = <0x8000>; /* 32 KiB */
76 d-cache-size = <0x8000>; /* 32 KiB */
79 i-cache-size = <0x8000>; /* 32 KiB */
89 cache-size = <0x80000>; /* 512 KiB */
[all …]
/linux/Documentation/driver-api/mtd/
H A Dspi-nor.rst33 1) Specify the controller that you used to test the flash and specify
41 root@1:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
43 root@1:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
45 root@1:~# cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
47 root@1:~# xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
51 1d81ed0f773830b030b0f7ffffff29c25cfff030c080ffffffffffffffff
69 root@1:~# sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
79 root@1:~# cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
81 1S-1S-1S
85 1S-1S-1S (fast read)
[all …]
/linux/tools/perf/arch/powerpc/util/
H A Dauxtrace.c17 #define KiB(x) ((x) * 1024) macro
31 opts->auxtrace_mmap_pages = KiB(128) / page_size; in powerpc_vpadtl_recording_options()
33 opts->mmap_pages = KiB(256) / page_size; in powerpc_vpadtl_recording_options()
75 found = 1; in auxtrace_record__init()
/linux/fs/jffs2/
H A Dbuild.c85 if (child_ic->pino_nlink > 1) in jffs2_build_inode_pass1()
86 *dir_hardlinks = 1; in jffs2_build_inode_pass1()
120 dbg_fsbuild("pass 1 starting\n"); in jffs2_build_filesystem()
130 dbg_fsbuild("pass 1 complete\n"); in jffs2_build_filesystem()
199 * value (which is 1). */ in jffs2_build_filesystem()
276 whinged = 1; in jffs2_build_remove_unlinked_inode()
327 size += c->sector_size - 1; /* ... and round up */ in jffs2_calc_trigger_levels()
333 c->resv_blocks_gctrigger = c->resv_blocks_write + 1; in jffs2_calc_trigger_levels()
337 c->resv_blocks_gcmerge = c->resv_blocks_deletion + 1; in jffs2_calc_trigger_levels()
355 dbg_fsbuild("trigger levels (size %d KiB, block size %d KiB, %d blocks)\n", in jffs2_calc_trigger_levels()
[all …]
/linux/include/linux/mtd/
H A Dspi-nor.h25 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
41 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
42 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
43 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
45 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
67 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
68 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
69 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
102 #define SR_WEL BIT(1) /* Write enable latch */
105 #define SR_BP1 BIT(3) /* Block protect 1 */
[all …]
/linux/Documentation/filesystems/nfs/
H A Drpc-server-gss.rst8 NFSv4.1 and higher don't require the client to act as a server for the
55 A) It can handle tokens that are no bigger than 2KiB
58 beyond 64KiB in size due to various authorization extensions attacked to
65 back to the kernel (4KiB).
85 to /var/run/gssproxy.sock and then write "1" to
93 "1"--the read will block until gss-proxy has done its write to the file.
/linux/Documentation/staging/
H A Dxz.rst48 which will use no BCJ filter and 1 MiB LZMA2 dictionary.
74 desktop systems while 64 KiB to 1 MiB might be more appropriate on
80 are allocated which take a little less than 30 KiB of memory.
91 xz --threads=1 --check=crc32 --lzma2=dict=512KiB inputfile
/linux/include/linux/
H A Dxz.h151 * or 2^n + 2^(n-1) bytes (the latter sizes are less common
153 * In the kernel, dictionary sizes of 64 KiB, 128 KiB, 256 KiB,
154 * 512 KiB, and 1 MiB are probably the only reasonable values,
252 * @dict_size: LZMA dictionary size. This must be at least 4 KiB and
259 * The amount of allocated memory is a little less than 30 KiB with XZ_SINGLE.
341 # define XZ_INTERNAL_CRC32 1
/linux/lib/
H A Ddecompress_unxz.c52 * may be up to 64 KiB of actual payload in the chunk. Often the payload is
54 * chunk has only 32 KiB of payload.
74 * - 8 bytes per every 32 KiB of uncompressed size (one LZMA2 chunk header
75 * per chunk, each chunk having average payload size of 32 KiB); and
76 * - 64 KiB (biggest possible LZMA2 chunk payload size) to make sure that
119 #define XZ_INTERNAL_CRC32 1
279 s = xz_dec_init(XZ_DYNALLOC, (uint32_t)-1); in unxz()
286 b.out_size = (size_t)-1; in unxz()
386 return -1; in unxz()
397 return -1; in unxz()
/linux/Documentation/gpu/
H A Dpanfrost.rst36 drm-resident-memory: 36496 KiB
37 drm-purgeable-memory: 128 KiB
49 Where `N` is either `0` or `1`, depending on the desired enablement status.
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dnv44.c39 * allocated on 512KiB alignment, and not exceed a total size in nv44_mmu_init()
40 * of 512KiB for this to work correctly in nv44_mmu_init()
43 addr -= ((nvkm_memory_addr(pt) >> 19) + 1) << 19; in nv44_mmu_init()
59 .mmu = {{ -1, -1, NVIF_CLASS_MMU_NV04}},
60 .mem = {{ -1, -1, NVIF_CLASS_MEM_NV04}, nv04_mem_new, nv04_mem_map },
61 .vmm = {{ -1, -1, NVIF_CLASS_VMM_NV04}, nv44_vmm_new, true },

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