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/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
64 # 7 chars 1 lines
[all …]
/linux/sound/ppc/
H A Dawacs.h25 unsigned byteswap; /* Data is little-endian if 1 */
45 #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */
56 #define MASK_ADDR1 (0x1 << 12) /* Expanded Data Mode Address 1 */
91 /* Address 1 Bit Masks */
98 #define MASK_CMUTE (0x1 << 7) /* Output C (Speaker) Mute when 1 */
102 #define MASK_AMUTE (0x1 << 9) /* Output A (Headphone) Mute when 1 */
112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
H A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
/linux/Documentation/sound/cards/
H A Daudiophile-usb.rst35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
125 way (I suppose the device's index is 1):
127 * hw:1,0 is Ao in playback and Di in capture
128 * hw:1,1 is Do in playback and Ai in capture
129 * hw:1,2 is Do in AC3/DTS passthrough mode
[all …]
/linux/tools/testing/selftests/alsa/
H A Dpcm-test.conf2 description "8kHz mono large periods"
6 channels 1
11 description "8kHz stereo large periods"
20 description "44.1kHz stereo large periods"
29 description "48kHz stereo small periods"
38 description "48kHz stereo large periods"
47 description "48kHz 6 channel large periods"
56 description "96kHz stereo large periods"
/linux/include/sound/
H A Ddesignware_i2s.h16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
27 #define DWC_I2S_PLAY (1 << 0)
28 #define DWC_I2S_RECORD (1 << 1)
29 #define DW_I2S_SLAVE (1 << 2)
30 #define DW_I2S_MASTER (1 << 3)
36 #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
37 #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1)
38 #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
/linux/sound/pci/ca0106/
H A Dca0106.h65 /* CNL[1:0], ADDR[27:16] */
71 /* Clear pending interrupts by writing a 1 to */
116 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */
117 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */
118 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12…
121 #define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */
122 #define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */
123 #define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */
124 #define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
[all …]
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_defs.h14 MXL_ENABLE = 1,
17 MXL_TRUE = 1,
20 MXL_VALID = 1,
23 MXL_YES = 1,
26 MXL_ON = 1
34 MXL_HYDRA_DEV_SET_POWER_MODE_CMD = 1,
132 #define MXL_HYDRA_SKU_ID_584 1
153 #define MBIN_FORMAT_VERSION '1'
156 #define MBIN_MAX_FILE_LENGTH (1<<23)
190 cmd_buff[1] = (size > 251) ? 0xff : (u8) (size + 4); \
[all …]
/linux/drivers/gpu/drm/radeon/
H A Datombios.h59 #define ATOM_DAC_B 1
63 #define ATOM_CRTC2 1
71 #define ATOM_DIGB 1
74 #define ATOM_PPLL2 1
85 #define ENCODER_REFCLK_SRC_P2PLL 1
91 #define ATOM_SCALER2 1
94 #define ATOM_SCALER_CENTER 1
99 #define ATOM_ENABLE 1
109 #define ATOM_BLANKING 1
113 #define ATOM_CURSOR2 1
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h58 #define ATOM_DAC_B 1
62 #define ATOM_CRTC2 1
74 #define ATOM_DIGB 1
77 #define ATOM_PPLL2 1
102 #define ENCODER_REFCLK_SRC_P2PLL 1
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
113 #define ATOM_ENABLE 1
123 #define ATOM_BLANKING 1
128 #define ATOM_CRT2 1
130 #define ATOM_TV_NTSC 1
[all …]
/linux/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
44 00:13.1 System peripheral: Intel Corporation Centerton SMBus 2.0 Controller 1
/linux/arch/arm/mach-omap1/
H A Dtimer32k.c59 * 32KHz OS timer
62 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
63 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
65 * with the 32KHz synchronized timer.
79 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
82 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
95 load_val = 1; in omap_32k_timer_start()
152 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) in omap_init_32k_timer()
153 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); in omap_init_32k_timer()
157 OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe); in omap_init_32k_timer()
[all …]
/linux/drivers/media/tuners/
H A Dtda9887.c46 #define UNSET (-1U)
101 #define cAudioIF_4_5 0x00 // bit e0:1
102 #define cAudioIF_5_5 0x01 // bit e0:1
103 #define cAudioIF_6_0 0x02 // bit e0:1
104 #define cAudioIF_6_5 0x03 // bit e0:1
118 /* IF1 selection in Radio Mode (bit B3=1) */
122 /* Output of AFC pin in radio mode when bit E7=1 */
276 "- 12.5 kHz", in dump_read_message()
277 "- 37.5 kHz", in dump_read_message()
278 "- 62.5 kHz", in dump_read_message()
[all …]
H A Dqt1010_priv.h24 09 10 ? changes every 8/24 MHz; values 1d/1c
35 14 1f ?
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
42 1b 00 ?
43 1c 89 ?
44 1d 00 ?
45 1e 00 ? looks like operation register; write cmd here, read result from 1f-26
46 1f 20 ? chip initialization
65 #define QT1010_STEP (125 * kHz) /*
75 #define QT1010_RD 1
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgt215.c112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll()
126 P = 1; in read_pll()
187 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz, in gt215_clk_info() argument
196 switch (khz) { in gt215_clk_info()
199 return khz; in gt215_clk_info()
202 return khz; in gt215_clk_info()
205 return khz; in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
210 diff = ((khz + 3000) - oclk); in gt215_clk_info()
235 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, in gt215_pll_info() argument
[all …]
/linux/drivers/net/wireless/st/cw1200/
H A Dmain.c58 MODULE_PARM_DESC(cw1200_power_mode, "WSM power mode. 0 == active, 1 == doze, 2 == quiescent (defau…
69 RATETAB_ENT(20, 1, 0),
120 CHAN2G(1, 2412, 0),
165 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT) |
167 .ht_supported = 1,
185 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT) |
187 .ht_supported = 1,
199 1 * HZ, /* VO */
242 static int cw1200_ba_rx_tids = -1;
243 static int cw1200_ba_tx_tids = -1;
[all …]
/linux/Documentation/hwmon/
H A Dlm85.rst105 Remote 1 is generally the CPU temperature. These inputs are designed to
153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
213 sensors and therefore three zones (# 1, 2 and 3). Each zone has the following
239 the behaviour of fans. Write 1 to let fans spinning at
260 1 Controlled by Zone 1
[all …]
/linux/sound/soc/codecs/
H A Dmax98363.c125 /* BITMAP: 00000010 Dataport 1 is active */ in max98363_read_prop()
126 prop->sink_ports = BIT(1); in max98363_read_prop()
223 port_config.num = 1; in max98363_sdw_dai_hw_params()
228 stream_config.ch_count = 1; in max98363_sdw_dai_hw_params()
235 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0); in max98363_sdw_dai_hw_params()
238 &port_config, 1, stream); in max98363_sdw_dai_hw_params()
285 .channels_min = 1,
286 .channels_max = 1,
317 static DECLARE_TLV_DB_SCALE(max98363_digital_tlv, -6350, 50, 1);
323 "Reserved", "0", "+FS/2", "-FS/2", "1KH
[all...]
H A Dwm8974.c33 { 0, 0x0000 }, { 1, 0x0000 }, { 2, 0x0000 }, { 3, 0x0000 },
56 static const char *wm8974_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" };
61 static const char *wm8974_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" };
62 static const char *wm8974_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" };
[all...]
/linux/sound/pci/emu10k1/
H A Dp16v.h41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
42 * 1 = Capture output 1.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
46 * 1 = Capture output 1.
50 * 1 = Capture output 1.
54 * 1 = Capture output 1.
58 * 1 = Play output 1.
61 * [11:10] Playback input 1 channel select. 0 = Play output 0.
62 * 1 = Play output 1.
66 * 1 = Play output 1.
[all …]
/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
29 /* kHz ignored */
48 /* kHz ignored */
67 /* kHz ignored */
86 /* kHz ignored */
116 interrupts = <1 13 0xf01>;
123 interrupts = <1 14 0xf01>;
/linux/sound/firewire/dice/
H A Ddice.c38 int key, val, vendor = -1, model = -1; in check_dice_category()
118 card->shortname[sizeof(card->shortname) - 1] = '\0'; in dice_card_strings()
157 err = snd_card_new(&unit->device, -1, NULL, THIS_MODULE, sizeof(*dice), &card); in dice_probe()
172 // Below models are compliant to IEC 61883-1/6 and have no quirk at high sampling transfer in dice_probe()
395 // Weiss DAC202: 192kHz 2-channel DAC
402 // Weiss DAC202: 192kHz 2-channel DAC (Maya edition)
409 // Weiss MAN301: 192kHz 2-channel music archive network player
416 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire face
423 // Weiss INT203: 192kHz bidirectiona
[all...]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q.dtsi16 #address-cells = <1>;
25 /* kHz uV */
33 /* ARM kHz SOC-PU uV */
56 cpu1: cpu@1 {
59 reg = <1>;
62 /* kHz uV */
70 /* ARM kHz SOC-PU uV */
97 /* kHz uV */
105 /* ARM kHz SOC-PU uV */
132 /* kHz uV */
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dwhite-hawk-ard-audio-da7212.dtso55 * 44.1kHz groups sound is available by default.
56 * You need to update audio_clkin settings to switch to 48kHz groups sound.
88 /* 44.1kHz groups [(C) clock] */
92 /* 48 kHz groups [(C) clock] */
124 #address-cells = <1>;
127 codec@1a {
159 clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */
160 // clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */

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