xref: /linux/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800) 
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
8
9maintainers:
10  - Sibi Sankar <quic_sibis@quicinc.com>
11
12description:
13  The CPUSS Control Processor (CPUCP) mailbox controller enables communication
14  between AP and CPUCP by acting as a doorbell between them.
15
16properties:
17  compatible:
18    items:
19      - const: qcom,x1e80100-cpucp-mbox
20
21  reg:
22    items:
23      - description: CPUCP rx register region
24      - description: CPUCP tx register region
25
26  interrupts:
27    maxItems: 1
28
29  "#mbox-cells":
30    const: 1
31
32required:
33  - compatible
34  - reg
35  - interrupts
36  - "#mbox-cells"
37
38additionalProperties: false
39
40examples:
41  - |
42    #include <dt-bindings/interrupt-controller/arm-gic.h>
43
44    mailbox@17430000 {
45        compatible = "qcom,x1e80100-cpucp-mbox";
46        reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
47        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
48        #mbox-cells = <1>;
49    };
50