| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu11_driver_if_sienna_cichlid.h | 34 #define NUM_GFXCLK_DPM_LEVELS 16
94 #define FEATURE_DS_DCEFCLK_BIT 16
211 #define THROTTLER_PPT3_BIT 16
267 #define RLC_PACE_TABLE_NUM_LEVELS 16
268 #define SIENNA_CICHLID_UMC_CHANNEL_NUM 16
295 #define NUM_I2C_CONTROLLERS 16
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
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| H A D | smu13_driver_if_aldebaran.h | 54 #define FEATURE_PPT_BIT 16
127 #define THORTTLER_SPARE_16 16
292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
348 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed]
349 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed]
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| H A D | smu11_driver_if_arcturus.h | 34 #define NUM_GFXCLK_DPM_LEVELS 16
74 #define FEATURE_PPT_BIT 16
203 #define THROTTLER_VRHOT0_BIT 16
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
452 XGMI_LINK_WIDTH_16 = 16, // x16
497 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
504 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
505 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
506 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
507 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
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| H A D | smu11_driver_if_navi10.h | 35 #define NUM_GFXCLK_DPM_LEVELS 16
89 #define FEATURE_FW_DSTATE_BIT 16
190 #define THROTTLER_PPT2_BIT 16
558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
576 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
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| H A D | smu13_driver_if_v13_0_0.h | 32 #define NUM_GFXCLK_DPM_LEVELS 16
64 #define FEATURE_DS_UCLK_BIT 16
202 #define THROTTLER_PPT0_BIT 16
227 #define FW_DSTATE_UCP_DS_BIT 16
263 DRAM_BIT_WIDTH_X_16 = 16,
863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
919 uint16_t DcTol; // mV Q2
920 uint16_t DcBtcGb; // mV Q2
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| H A D | smu13_driver_if_v13_0_7.h | 33 #define NUM_GFXCLK_DPM_LEVELS 16
65 #define FEATURE_DS_UCLK_BIT 16
203 #define THROTTLER_PPT0_BIT 16
228 #define FW_DSTATE_UCP_DS_BIT 16
264 DRAM_BIT_WIDTH_X_16 = 16,
872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
928 uint16_t DcTol; // mV Q2
929 uint16_t DcBtcGb; // mV Q2
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| H A D | smu14_driver_if_v14_0.h | 30 #define NUM_GFXCLK_DPM_LEVELS 16
62 #define FEATURE_GFX_ULV_BIT 16
211 #define THROTTLER_PPT2_BIT 16
235 #define FW_DSTATE_CLDO_PRG_BIT 16
264 DRAM_BIT_WIDTH_X_16 = 16,
757 uint16_t VddGfxVmax; // in mV
820 uint16_t VddGfxVmax; // in mV
964 uint16_t InitGfx; // In mV(Q2) , should be 0?
965 uint16_t InitSoc; // In mV(Q2)
966 uint16_t InitVddIoMem; // In mV(Q2) MemVdd
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | cs35l33.txt | 22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
24 8000mV.
55 depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
62 stage enters LDO operation. Starts as a default value of 50mV for a value
63 of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
81 by 100mV per step to a maximum of 5500mV.
91 1800mV with a step size of 50mV up to a maximum value of 1750mV.
92 Default is 1800mV.
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| /linux/drivers/media/platform/rockchip/rkvdec/ |
| H A D | rkvdec-vp9.c | 58 u8 padding5[16];
69 } mv; member
73 u8 partition[16][3];
103 u32 partition[16][4];
290 /* mv related 6 x 128 */ in init_inter_probs()
291 memcpy(rkprobs->mv.joint, probs->mv.joint, in init_inter_probs()
292 sizeof(rkprobs->mv.joint)); in init_inter_probs()
293 memcpy(rkprobs->mv.sign, probs->mv.sign, in init_inter_probs()
294 sizeof(rkprobs->mv.sign)); in init_inter_probs()
295 memcpy(rkprobs->mv.classes, probs->mv.classes, in init_inter_probs()
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| /linux/drivers/iio/adc/ |
| H A D | ti-ads1018.c | 74 * gain = 6144 / 2^(16 - 1) = 0.1875
110 .storagebits = 16, \
111 .shift = 16 - _realbits, \
130 .storagebits = 16, \
131 .shift = 16 - _realbits, \
148 .storagebits = 16, \
149 .shift = 16 - _realbits, \
159 ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 16),
160 ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 16),
161 ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 16),
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| /linux/arch/riscv/kernel/ |
| H A D | mcount.S | 18 addi sp, sp, -16
21 addi s0, sp, 16
40 addi sp, sp, 16
71 * value stored in -16(s0) on entry, and the s0 on return.
74 mv a0, sp
76 mv a2, a0
107 mv a1, ra
123 mv a0, ra
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| H A D | mcount-dyn.S | 19 #define ABI_A2 16
108 mv a0, sp
143 mv a1, ra // parent_ip
144 REG_L a2, -16(t0) // op
149 mv a1, ra // parent_ip
151 mv a3, sp // regs
172 * so we find the associated op at t0-16.
174 REG_L t1, -16(t0) // op Should be SZ_REG instead of 16
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| /linux/drivers/scsi/ |
| H A D | ch.c | 37 #define CH_DT_MAX 16
264 if (((buffer[16] << 8) | buffer[17]) != elem) { in ch_read_element_status()
266 elem,(buffer[16] << 8) | buffer[17]); in ch_read_element_status()
270 memcpy(data,buffer+16,16); in ch_read_element_status()
301 u_char cmd[10], data[16]; in ch_readconfig()
332 (buffer[buffer[3]+16] << 8) | buffer[buffer[3]+17]; in ch_readconfig()
547 u_char data[16]; in ch_gstatus()
710 struct changer_move mv; in ch_ioctl() local
712 if (copy_from_user(&mv, argp, sizeof (mv))) in ch_ioctl()
715 if (0 != ch_checkrange(ch, mv.cm_fromtype, mv.cm_fromunit) || in ch_ioctl()
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| /linux/Documentation/devicetree/bindings/regulator/ |
| H A D | maxim,max8952.yaml | 46 - 0: 32mV/us
47 - 1: 16mV/us
48 - 2: 8mV/us
49 - 3: 4mV/us
50 - 4: 2mV/us
51 - 5: 1mV/us
52 - 6: 0.5mV/us
53 - 7: 0.25mV/us
54 Defaults to 32mV/us if not specified.
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| /linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/ |
| H A D | vdec_vp9_req_lat_if.c | 42 u8 y_mode_prob[4][16];
43 u8 switch_interp_prob[4][16];
45 u8 comp_inter_prob[16];
46 u8 comp_ref_prob[16];
70 u8 uv_mode_prob[10][16];
71 u8 uv_mode_prob_padding[2][16];
73 u8 partition_prob[16][4];
112 u32 partition[16][4];
340 * @mv: mv working buffer
359 struct vdec_vp9_slice_mem mv[2]; member
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| /linux/drivers/media/v4l2-core/ |
| H A D | v4l2-vp9.c | 45 { 44, 24, 16, 150, 177, 202, 33, 19, 156 }, /*left = d153*/
88 { 46, 16, 24, 136, 76, 147, 41, 64, 172 }, /*left = d117*/
101 { 68, 26, 16, 111, 141, 215, 29, 28, 28 }, /*left = d207*/
130 const u8 v4l2_vp9_kf_partition_probs[16][3] = {
136 /* 16x16 -> 8x8 */
141 /* 32x32 -> 16x16 */
281 { 3, 16, 42 },
301 { 1, 16, 28 },
594 { /* tx = 16x16 */
600 { 1, 16, 30 },
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| /linux/tools/power/cpupower/debug/i386/ |
| H A D | centrino-decode.c | 66 unsigned int mv; in decode() local
70 mv = (((msr & 0xFF) * 16) + 700); in decode()
72 printf("0x%x means multiplier %d @ %d mV\n", msr, multiplier, mv); in decode()
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| /linux/drivers/hwmon/ |
| H A D | ltc2945.c | 82 /* Return the value from the given register in uW, mV, or mA */
100 val = (buf[0] << 16) + (buf[1] << 8) + buf[2]; in ltc2945_reg_to_val()
121 /* 25 mV * 25 uV = 0.625 uV resolution. */ in ltc2945_reg_to_val()
124 /* 0.5 mV * 25 uV = 0.0125 uV resolution. */ in ltc2945_reg_to_val()
141 /* 25 mV resolution. Convert to mV. */ in ltc2945_reg_to_val()
149 /* 0.5mV resolution. Convert to mV. */ in ltc2945_reg_to_val()
196 /* 25 mV * 25 uV = 0.625 uV resolution. */ in ltc2945_val_to_reg()
202 /* 0.5 mV * 25 uV = 0.0125 uV resolution. */ in ltc2945_val_to_reg()
214 /* 25 mV resolution. */ in ltc2945_val_to_reg()
222 /* 0.5mV resolution. */ in ltc2945_val_to_reg()
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| /linux/drivers/cpufreq/ |
| H A D | longhaul.c | 61 static unsigned int numscales = 16;
128 invalue += 16; in longhaul_get_cpu_mult()
557 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) { in longhaul_setup_voltagescaling()
559 minvid.mV/1000, minvid.mV%1000, in longhaul_setup_voltagescaling()
560 maxvid.mV/1000, maxvid.mV%1000); in longhaul_setup_voltagescaling()
564 if (minvid.mV == maxvid.mV) { in longhaul_setup_voltagescaling()
566 maxvid.mV/1000, maxvid.mV%1000); in longhaul_setup_voltagescaling()
573 maxvid.mV/1000, maxvid.mV%1000, in longhaul_setup_voltagescaling()
574 minvid.mV/1000, minvid.mV%1000, in longhaul_setup_voltagescaling()
580 j += 16; in longhaul_setup_voltagescaling()
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| H A D | e_powersaver.c | 116 while (lo & ((1 << 16) | (1 << 17))) { in eps_set_state()
117 udelay(16); in eps_set_state()
129 udelay(16); in eps_set_state()
135 } while (lo & ((1 << 16) | (1 << 17))); in eps_set_state()
144 pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700); in eps_set_state()
242 pr_info("Current voltage = %dmV\n", current_voltage * 16 + 700); in eps_cpu_init()
248 pr_info("Highest voltage = %dmV\n", max_voltage * 16 + 700); in eps_cpu_init()
251 min_voltage = (hi >> 16) & 0xff; in eps_cpu_init()
252 pr_info("Lowest voltage = %dmV\n", min_voltage * 16 + 700); in eps_cpu_init()
307 /* Change mV to something hardware can use */ in eps_cpu_init()
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| /linux/drivers/hwmon/pmbus/ |
| H A D | mp2869.c | 64 static const int mp2869_iout_sacle[8] = {32, 1, 2, 4, 8, 16, 32, 64};
126 * 000b - 6.25mV/LSB, 001b - 5mV/LSB, 010b - 2.5mV/LSB, 011b - 2mV/LSB in mp2869_identify_vout_scale()
127 * 100b - 1mV/Lsb, 101b - (1/256)mV/LSB, 110b - (1/512)mV/LSB, in mp2869_identify_vout_scale()
128 * 111b - (1/1024)mV/LSB in mp2869_identify_vout_scale()
155 * 000b - 1A/LSB, 001b - (1/32)A/LSB, 010b - (1/16)A/LSB, in mp2869_identify_iout_scale()
265 * 31.25mV/LSB. And the vin scale is set to 31.25mV/Lsb(using r/m/b scale) in mp2869_read_word_data()
492 * should not be changed. The scale of PMBUS_VIN_OV_FAULT_LIMIT is 125mV/Lsb, in mp2869_write_word_data()
493 * but the vin scale is set to 31.25mV/Lsb(using r/m/b scale), so the word data in mp2869_write_word_data()
510 * not be changed. The scale of PMBUS_VIN_UV_LIMIT is 31.25mV/Lsb, and the in mp2869_write_word_data()
511 * vin scale is set to 31.25mV/Lsb(using r/m/b scale), so the word data can in mp2869_write_word_data()
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| H A D | mp2891.c | 101 * 2.5mV/LSB in mp2891_identify_vout_scale()
104 * 00b - 6.25mV/LSB, 01b - 5mV/LSB, 10b - 2mV/LSB, 11b - 1mV in mp2891_identify_vout_scale()
143 * 000b - 1A/LSB, 001b - (1/32)A/LSB, 010b - (1/16)A/LSB, in mp2891_identify_iout_scale()
165 data->iout_scale[page] = 16; in mp2891_identify_iout_scale()
310 * The MP2891 PMBUS_VIN_OV_FAULT_LIMIT scale is 125mV/Lsb. in mp2891_read_word_data()
311 * but the vin scale is set to 31.25mV/Lsb(using r/m/b scale). in mp2891_read_word_data()
454 * should not be changed. The scale of PMBUS_VIN_OV_FAULT_LIMIT is 125mV/Lsb, in mp2891_write_word_data()
455 * but the vin scale is set to 31.25mV/Lsb(using r/m/b scale), so the word data in mp2891_write_word_data()
527 /* set vin scale 31.25mV/Lsb */
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| /linux/Documentation/hwmon/ |
| H A D | w83793.rst | 48 voltage0-2 is 2mV, resolution of voltage3/4/5 is 16mV, 8mV for voltage6,
49 24mV for voltage7/8. Temp1-4 have a 0.25 degree Celsius resolution,
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| /linux/drivers/media/pci/tw5864/ |
| H A D | tw5864-reg.h | 92 /* MV Vector Valid */
94 /* MV Flag Valid */
138 * If DSP_MB_WAIT == 0, MB delay is DSP_MB_DELAY * 16
165 /* SENIF_ORG_FRM_PTR [31:16] */
174 * [15:0]: ENC_BUF_PTR_REC[31:16] Two bit for each channel (channel 8 ~ 15).
179 /* Current MV Flag Status Pointer for Channel n. (Read only) */
190 * [15:0] Reset Current MV Flag Status Pointer for Channel n (one bit each)
313 * 0x6 Only 16x16
314 * 0x7 16x16 & 4x4
424 * 0 Swap (VLC output={[23:16],[31:24],[7:0], [15:8]})
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| /linux/drivers/mfd/ |
| H A D | menelaus.c | 163 void (*handlers[16])(struct menelaus_chip *);
448 static int menelaus_set_voltage(const struct menelaus_vtg *vtg, int mV, in menelaus_set_voltage() argument
463 "to %d mV (reg 0x%02x, val 0x%02x)\n", in menelaus_set_voltage()
464 vtg->name, mV, vtg->vtg_reg, val); in menelaus_set_voltage()
516 { 1400, 16 },
535 dev_dbg(&c->dev, "Setting VCORE FLOOR to %d mV and ROOF to %d mV\n", in menelaus_set_vcore_hw()
573 int menelaus_set_vmem(unsigned int mV) in menelaus_set_vmem() argument
577 if (mV == 0) in menelaus_set_vmem()
580 val = menelaus_get_vtg_value(mV, vmem_values, ARRAY_SIZE(vmem_values)); in menelaus_set_vmem()
583 return menelaus_set_voltage(&vmem_vtg, mV, val, 0x02); in menelaus_set_vmem()
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