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/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l33.txt22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
24 8000mV.
39 ADC data word. This property can be set as a value of 0 for bits 15 down
62 stage enters LDO operation. Starts as a default value of 50mV for a value
63 of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
81 by 100mV per step to a maximum of 5500mV.
91 1800mV with a step size of 50mV up to a maximum value of 1750mV.
92 Default is 1800mV.
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-stm32-usbphyc.yaml110 - <1> increases the level by 5 to 7 mV
111 - <2> increases the level by 10 to 14 mV
112 - <3> decreases the level by 5 to 7 mV
144 - <15> = 23.348 mA target current / nominal + 23.73%
147 maximum: 15
166 - <1> = threshold shift by +7 mV
167 - <2> = threshold shift by -5 mV
168 - <3> = threshold shift by +14 mV
182 - <1> = offset of +5 mV
183 - <2> = offset of +10 mV
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_aldebaran.h53 #define FEATURE_WAFL_CG_BIT 15
126 #define THORTTLER_SPARE_15 15
292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
348 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed]
349 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed]
[all …]
H A Dsmu13_driver_if_v13_0_0.h63 #define FEATURE_DS_DCFCLK_BIT 15
201 #define THROTTLER_TDC_U_BIT 15
226 #define FW_DSTATE_U_PSI_BIT 15
863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
919 uint16_t DcTol; // mV Q2
920 uint16_t DcBtcGb; // mV Q2
922 uint16_t DcBtcMin; // mV Q2
923 uint16_t DcBtcMax; // mV Q2
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H A Dsmu13_driver_if_v13_0_7.h64 #define FEATURE_DS_DCFCLK_BIT 15
202 #define THROTTLER_TDC_U_BIT 15
227 #define FW_DSTATE_U_PSI_BIT 15
872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
928 uint16_t DcTol; // mV Q2
929 uint16_t DcBtcGb; // mV Q2
931 uint16_t DcBtcMin; // mV Q2
932 uint16_t DcBtcMax; // mV Q2
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H A Dsmu14_driver_if_v14_0.h61 #define FEATURE_DS_UCLK_BIT 15
210 #define THROTTLER_PPT1_BIT 15
234 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 15
600 MEM_VENDOR_MICRON, // 15
757 uint16_t VddGfxVmax; // in mV
820 uint16_t VddGfxVmax; // in mV
964 uint16_t InitGfx; // In mV(Q2) , should be 0?
965 uint16_t InitSoc; // In mV(Q2)
966 uint16_t InitVddIoMem; // In mV(Q2) MemVdd
967 uint16_t InitVddCiMem; // In mV(Q2) VMemP
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H A Dsmu11_driver_if_arcturus.h72 #define FEATURE_WAFL_CG_BIT 15
202 #define THROTTLER_APCC_BIT 15
497 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
504 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
505 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
506 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
507 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
526 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
583 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
588 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2
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H A Dsmu11_driver_if_navi10.h88 #define FEATURE_GFX_ULV_BIT 15
189 #define THROTTLER_PPT1_BIT 15
558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
576 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
577 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h93 #define FEATURE_DS_LCLK_BIT 15
210 #define THROTTLER_PPT2_BIT 15
633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
647 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
649 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
650 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
652 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC
659 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
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/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-spi-slot.yaml32 Two cells are required, first cell specifies minimum slot voltage (mV),
33 second cell specifies maximum slot voltage (mV).
37 value for minimum slot voltage in mV
40 value for maximum slot voltage in mV
69 gpios = <&gpio 14 GPIO_ACTIVE_LOW>, <&gpio 15 GPIO_ACTIVE_HIGH>;
/linux/drivers/media/v4l2-core/
H A Dv4l2-vp9.c41 { 42, 26, 11, 199, 241, 228, 23, 15, 85 }, /*left = h */
89 { 34, 17, 11, 108, 152, 187, 13, 15, 209 }, /*left = d153*/
100 { 51, 25, 15, 136, 129, 202, 38, 35, 139 }, /*left = d153*/
149 { 57, 15, 9 }, /* l split, a not split */
156 { 118, 15, 123, 148, 131, 101, 44, 93, 131 }, /* y = v */
175 { 15, 101 },
212 { 15, 91, 159 },
223 { 1, 15, 29 },
314 { 15, 97, 179 },
507 { 1, 15, 25 },
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h12 /* [15:0] The Version register for H264 core (Read Only) */
49 #define TW5864_START_NSLICE BIT(15)
52 * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
57 /* [5:0] DSP_MB_QP and [15:10] DSP_LPF_OFFSET */
63 * [15:10] H264 LPF_OFFSET Address
92 /* MV Vector Valid */
94 /* MV Flag Valid */
120 /* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */
160 #define TW5864_DDR_MODE BIT(15)
163 /* SENIF_ORG_FRM_PTR [15:0] */
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dadi,ltc4282.yaml58 10% and 15% settings with the actual min, typical and max tolerances.
70 10% and 15% settings with the actual min, typical and max tolerances.
78 12.5mV and 34.4mV in 3.1mV steps. This effectively limits the current
/linux/Documentation/hwmon/
H A Dmc13783-adc.rst31 A/D converter has a resolution of 2.25mV.
48 1 Battery Current (BATT - BATTISNS) -50 - 50 mV x20
65 15 General Purpose TSY2 / Touchscreen Y-plate 2 0 - 2.30V No
74 1 Battery Current (BATT - BATTISNSCC) -60 - 60 mV x20
88 15 General Purpose TSY2 / Touchscreen Y-plate 2 0 - 2.4V No
/linux/Documentation/translations/zh_CN/filesystems/
H A Dinotify.rst17 文档由 Robert Love <rml@novell.com> 于 2005 年 3 月 15 日开始撰写
52 序（如 Beagle）至关重要。想象一下，如果“mv a b ; mv b a”这样的事件没有顺序会是什么
/linux/Documentation/devicetree/bindings/regulator/
H A Dmediatek,mt6397-regulator.yaml24 "^(buck_)?v(core|drm|gpu|io18|pca(7|15)|sramca(7|15))$":
38 description: LDOs with fixed 2.8V output and 0~100/10mV tuning
46 description: LDOs with fixed 3.0V output and 0~100/10mV tuning
54 description: LDOs with variable output and 0~100/10mV tuning
/linux/drivers/mfd/
H A Dmenelaus.c115 #define MENELAUS_RESERVED15_IRQ 15 /* Reserved */
448 static int menelaus_set_voltage(const struct menelaus_vtg *vtg, int mV, in menelaus_set_voltage() argument
463 "to %d mV (reg 0x%02x, val 0x%02x)\n", in menelaus_set_voltage()
464 vtg->name, mV, vtg->vtg_reg, val); in menelaus_set_voltage()
515 { 1375, 15 },
535 dev_dbg(&c->dev, "Setting VCORE FLOOR to %d mV and ROOF to %d mV\n", in menelaus_set_vcore_hw()
573 int menelaus_set_vmem(unsigned int mV) in menelaus_set_vmem() argument
577 if (mV == 0) in menelaus_set_vmem()
580 val = menelaus_get_vtg_value(mV, vmem_values, ARRAY_SIZE(vmem_values)); in menelaus_set_vmem()
583 return menelaus_set_voltage(&vmem_vtg, mV, val, 0x02); in menelaus_set_vmem()
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/linux/drivers/iio/adc/
H A Drzn1-adc.c45 #define RZN1_ADC_VC_ADC1_ENABLE BIT(15)
96 RZN1_ADC_CHANNEL_SHARED_SCALE(15, "ADC2_IN8"),
119 RZN1_ADC_CHANNEL_SEPARATED_SCALE(15, "ADC2_IN8"),
126 int adc1_vref_mV; /* ADC1 Vref in mV. Negative if ADC1 is not used */
127 int adc2_vref_mV; /* ADC2 Vref in mV. Negative if ADC2 is not used */
243 /* chan 8..15 used to get ADC2 ch 0..7 */ in rzn1_adc_read_raw_ch()
283 /* chan 8..15 use ADC2 ch 0..7. Vref related to ADC2 core */ in rzn1_adc_get_vref_mV()
365 * the ADC core is not used. Otherwise it is set to the VRef mV value. in rzn1_adc_core_get_regulators()
386 * Set adc_vref_mV to the Vref value in mV. This, as the value set is in rzn1_adc_core_get_regulators()
H A Dti-ads1018.c29 #define ADS1018_CFG_OS_TRIG BIT(15)
686 { 3, 0 }, /* fsr = 6144 mV */
687 { 2, 0 }, /* fsr = 4096 mV */
688 { 1, 0 }, /* fsr = 2048 mV */
689 { 0, 500000000 }, /* fsr = 1024 mV */
690 { 0, 250000000 }, /* fsr = 512 mV */
691 { 0, 125000000 }, /* fsr = 256 mV */
703 { 0, 187500000 }, /* fsr = 6144 mV */
704 { 0, 125000000 }, /* fsr = 4096 mV */
705 { 0, 62500000 }, /* fsr = 2048 mV */
[all …]
/linux/drivers/cpufreq/
H A Dlonghaul.c557 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) { in longhaul_setup_voltagescaling()
559 minvid.mV/1000, minvid.mV%1000, in longhaul_setup_voltagescaling()
560 maxvid.mV/1000, maxvid.mV%1000); in longhaul_setup_voltagescaling()
564 if (minvid.mV == maxvid.mV) { in longhaul_setup_voltagescaling()
566 maxvid.mV/1000, maxvid.mV%1000); in longhaul_setup_voltagescaling()
573 maxvid.mV/1000, maxvid.mV%1000, in longhaul_setup_voltagescaling()
574 minvid.mV/1000, minvid.mV%1000, in longhaul_setup_voltagescaling()
610 pr_info("f: %d kHz, index: %d, vid: %d mV\n", in longhaul_setup_voltagescaling()
611 speed, j, vid.mV); in longhaul_setup_voltagescaling()
787 case 1 ... 15: in longhaul_cpu_init()
[all …]
/linux/drivers/iio/dac/
H A Dstm32-dac-core.h23 #define STM32H7_DAC_CR_HFSEL BIT(15)
29 * @vref_mv: reference voltage (mv)
/linux/drivers/scsi/
H A Dch.c330 (buffer[buffer[3]+14] << 8) | buffer[buffer[3]+15]; in ch_readconfig()
710 struct changer_move mv; in ch_ioctl() local
712 if (copy_from_user(&mv, argp, sizeof (mv))) in ch_ioctl()
715 if (0 != ch_checkrange(ch, mv.cm_fromtype, mv.cm_fromunit) || in ch_ioctl()
716 0 != ch_checkrange(ch, mv.cm_totype, mv.cm_tounit )) { in ch_ioctl()
723 ch->firsts[mv.cm_fromtype] + mv.cm_fromunit, in ch_ioctl()
724 ch->firsts[mv.cm_totype] + mv.cm_tounit, in ch_ioctl()
725 mv.cm_flags & CM_INVERT); in ch_ioctl()
732 struct changer_exchange mv; in ch_ioctl() local
734 if (copy_from_user(&mv, argp, sizeof (mv))) in ch_ioctl()
[all …]
/linux/Documentation/filesystems/
H A Dinotify.rst9 Document started 15 Mar 2005 by Robert Love <rml@novell.com>
54 "mv a b ; mv b a" events without ordering.
/linux/drivers/regulator/
H A Dtwl-regulator.c39 /* voltage in mV = table[VSEL]; table_len must be a power-of-two */
355 /* 600mV to 1450mV in 12.5 mV steps */
360 /* 600mV to 1450mV in 12.5 mV steps, everything above = 1500mV */
369 int mV = info->table[index]; in twl4030ldo_list_voltage() local
371 return IS_UNSUP(info, mV) ? 0 : (LDO_MV(mV) * 1000); in twl4030ldo_list_voltage()
531 TWL4030_ADJUSTABLE_SMPS(VDD1, 0x55, 15, 1000, 0x08, 68);
/linux/sound/soc/codecs/
H A Dtlv320adc3xxx.c348 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 },
499 { 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 },
645 "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "10
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