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Searched +full:1400 +full:mhz (Results 1 – 25 of 28) sorted by relevance

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/linux/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
H A Dpowernow-k8.h89 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
91 * - the parts can only step at <= 200 MHz intervals, odd fid values are
101 #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
242 /* Set maximum frequency as 1000MHz */
[all …]
/linux/drivers/soc/samsung/
H A Dexynos5422-asv.c26 * contains frequency value in MHz and subsequent columns contain the CPU
52 { 1400, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500,
94 { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,
136 { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,
172 { 1400, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
236 { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
266 { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
/linux/arch/arm/boot/dts/ti/omap/
H A Ddm814x-clocks.dtsi209 /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
275 /* L4_HS 220 MHz*/
293 /* L4_LS 110 MHz */
352 alwon_cm: alwon_cm@1400 {
/linux/drivers/clk/mvebu/
H A Dap806-system-controller.c67 *cpuclk_freq = 1400; in ap806_get_sar_clocks()
191 /* Fixed clock is always 1200 Mhz */ in ap806_syscon_common_probe()
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi163 capacity-dmips-mhz = <740>;
178 capacity-dmips-mhz = <740>;
193 capacity-dmips-mhz = <1024>;
208 capacity-dmips-mhz = <1024>;
1083 ovl0: ovl@1400c000 {
1093 ovl1: ovl@1400d000 {
1103 rdma0: rdma@1400e000 {
1113 rdma1: rdma@1400f000 {
H A Dmt8192.dtsi76 capacity-dmips-mhz = <427>;
95 capacity-dmips-mhz = <427>;
114 capacity-dmips-mhz = <427>;
133 capacity-dmips-mhz = <427>;
152 capacity-dmips-mhz = <1024>;
171 capacity-dmips-mhz = <1024>;
190 capacity-dmips-mhz = <1024>;
209 capacity-dmips-mhz = <1024>;
1548 ccorr0: ccorr@1400a000 {
1557 aal0: aal@1400b000 {
[all …]
/linux/drivers/iio/light/
H A Dadux1020.c193 { 1400, 0 },
255 /* Enable 32MHz clock */ in adux1020_read_fifo()
270 /* Set 32MHz clock to be controlled by internal state machine */ in adux1020_read_fifo()
676 "0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400");
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp.dtsi39 sdramc: sdramc@1400 {
230 /* 25 MHz reference crystal */
H A Darmada-xp-98dx3236.dtsi103 sdramc: sdramc@1400 {
265 /* 25 MHz reference crystal */
H A Darmada-38x.dtsi106 sdramc: sdramc@1400 {
725 /* 25 MHz reference crystal */
/linux/drivers/pmdomain/qcom/
H A Dcpr.c977 freq_diff /= 1000000; /* Convert to MHz */ in cpr_calculate_scaling()
1011 * max_volt_scale has units of uV/MHz while freq values in cpr_interpolate()
1132 * freq(corner_N): max frequency in MHz supported by fuse corner N in cpr_corner_init()
1133 * freq(corner_N-1): max frequency in MHz supported by fuse corner in cpr_corner_init()
1142 * freq_max: max frequency in MHz supported by the fuse corner in cpr_corner_init()
1143 * freq_corner: frequency in MHz corresponding to the corner in cpr_corner_init()
1372 .max_quot_scale = 1400,
1385 .max_quot_scale = 1400,
/linux/drivers/comedi/drivers/
H A Ddas16.c36 * [3] - master clock speed in MHz (optional, 1 or 10, ignored if
56 * 4922.PDF (das-1400)
57 * 4923.PDF (das1200, 1400, 1600)
1029 "Invalid option. Master clock must be set to 1 or 10 (MHz)\n"); in das16_attach()
/linux/arch/powerpc/crypto/
H A Daes-spe-glue.c33 * included. Even with the low end model clocked at 667 MHz this equals to a
35 * process a 512 byte disk block in one or a large 1400 bytes IPsec network
/linux/drivers/phy/cadence/
H A Dcdns-dphy.c114 870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500
382 * 1MHz clk (or something close). in cdns_dphy_power_on()
/linux/sound/soc/codecs/
H A Drtq9124.c105 4, 6, TLV_DB_SCALE_ITEM(1400, 200, 0));
279 dev_err(dev, "Bitrate exceed the internal PLL 24.576MHz (%d)\n", bitrate); in rtq9124_dai_hw_params()
H A Drt5514.c280 7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
492 * 1MHz - 3MHz range.
505 /* find divider that gives DMIC frequency below 3.072MHz */ in rt5514_calc_dmic_clk()
H A Dmax98090.c304 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
2002 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) in max98090_dai_set_sysclk()
2003 * 0x02 (when master clk is 20MHz to 40MHz).. in max98090_dai_set_sysclk()
2004 * 0x03 (when master clk is 40MHz to 60MHz).. in max98090_dai_set_sysclk()
/linux/drivers/net/wireless/ath/ath6kl/
H A Dwmi.h865 /* channels in Mhz */
891 /* channels in Mhz */
1375 /* channel in Mhz */
1672 __le16 ch; /* frequency in MHz */
1741 #define MAX_OPT_DATA_LEN 1400
/linux/drivers/media/dvb-frontends/
H A Dstb0899_drv.c136 { 1400, 501 },
1432 /* checking Search Range is meaningless for a fixed 3 Mhz */ in stb0899_search()
1575 .frequency_min_hz = 950 * MHz,
1576 .frequency_max_hz = 2150 * MHz,
/linux/drivers/net/ieee802154/
H A Dmcr20a.c499 /* freqency = ((PLL_INT+64) + (PLL_FRAC/65536)) * 32 MHz */ in mcr20a_set_channel()
611 -3000, -2800, -2600, -2400, -2200, -2000, -1800, -1600, -1400,
/linux/drivers/gpu/drm/i915/display/
H A Dintel_psr.c1316 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ in _compute_psr2_sdp_prior_scanline_indication()
1944 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || in intel_psr_enable_source()
1951 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) in intel_psr_enable_source()
2169 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) in intel_psr_disable_locked()
2690 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || in intel_psr_apply_su_area_workarounds()
/linux/drivers/video/fbdev/aty/
H A Datyfb_base.c287 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
961 * This code has been tested on a laptop with it's 1400x1050 LCD in aty_var_to_crtc()
1392 DPRINTK(" Dot clock: %i MHz\n", in atyfb_set_par()
2436 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ in aty_init()
2588 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n", in aty_init()

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