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Searched +full:1400 +full:mhz (Results 1 – 25 of 48) sorted by relevance

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/linux/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
H A Dspeedstep-centrino.c83 frequency/voltage operating point; frequency in MHz, volts in mV.
85 #define OP(mhz, mv) \ argument
87 .frequency = (mhz) * 1000, \
88 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
98 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
107 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
159 OP(1400, 1484),
170 OP(1400, 1452),
182 OP(1400, 1420),
194 OP(1400, 1308),
[all …]
H A Dpowernow-k8.h89 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
91 * - the parts can only step at <= 200 MHz intervals, odd fid values are
101 #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
H A Dpowernow-k7.c72 1600, 1550, 1500, 1450, 1400, 1350, 1300, 0,
358 pr_debug("acpi: P%d: %d MHz %d mW %d uS control %08x SGTC %d\n", in powernow_acpi_init()
376 /* processor_perflib will multiply the MHz value by 1000 to in powernow_acpi_init()
380 * ACPI doesn't restrict them, so we round up the MHz value in powernow_acpi_init()
637 pr_info("Minimum speed %d MHz - Maximum speed %d MHz\n", in powernow_cpu_init()
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
242 /* Set maximum frequency as 1000MHz */
[all …]
/linux/drivers/soc/samsung/
H A Dexynos5422-asv.c26 * contains frequency value in MHz and subsequent columns contain the CPU
52 { 1400, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500,
94 { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,
136 { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,
172 { 1400, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
236 { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
266 { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
/linux/arch/arm/boot/dts/ti/omap/
H A Ddm814x-clocks.dtsi209 /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
275 /* L4_HS 220 MHz*/
293 /* L4_LS 110 MHz */
352 alwon_cm: alwon_cm@1400 {
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186.dtsi378 capacity-dmips-mhz = <382>;
402 capacity-dmips-mhz = <382>;
426 capacity-dmips-mhz = <382>;
450 capacity-dmips-mhz = <382>;
474 capacity-dmips-mhz = <382>;
498 capacity-dmips-mhz = <382>;
522 capacity-dmips-mhz = <1024>;
546 capacity-dmips-mhz = <1024>;
577 min-residency-us = <1400>;
1854 dpi: dpi@1400a000 {
[all …]
H A Dmt8173.dtsi163 capacity-dmips-mhz = <740>;
178 capacity-dmips-mhz = <740>;
193 capacity-dmips-mhz = <1024>;
208 capacity-dmips-mhz = <1024>;
1074 ovl0: ovl@1400c000 {
1084 ovl1: ovl@1400d000 {
1094 rdma0: rdma@1400e000 {
1104 rdma1: rdma@1400f000 {
H A Dmt8192.dtsi76 capacity-dmips-mhz = <427>;
95 capacity-dmips-mhz = <427>;
114 capacity-dmips-mhz = <427>;
133 capacity-dmips-mhz = <427>;
152 capacity-dmips-mhz = <1024>;
171 capacity-dmips-mhz = <1024>;
190 capacity-dmips-mhz = <1024>;
209 capacity-dmips-mhz = <1024>;
1548 ccorr0: ccorr@1400a000 {
1557 aal0: aal@1400b000 {
[all …]
H A Dmt8183.dtsi332 capacity-dmips-mhz = <741>;
355 capacity-dmips-mhz = <741>;
378 capacity-dmips-mhz = <741>;
401 capacity-dmips-mhz = <741>;
424 capacity-dmips-mhz = <1024>;
447 capacity-dmips-mhz = <1024>;
470 capacity-dmips-mhz = <1024>;
493 capacity-dmips-mhz = <1024>;
1747 ovl_2l1: ovl@1400a000 {
1757 rdma0: rdma@1400b000 {
[all …]
/linux/drivers/clk/mvebu/
H A Dap806-system-controller.c67 *cpuclk_freq = 1400; in ap806_get_sar_clocks()
191 /* Fixed clock is always 1200 Mhz */ in ap806_syscon_common_probe()
/linux/drivers/iio/light/
H A Dadux1020.c195 { 1400, 0 },
257 /* Enable 32MHz clock */ in adux1020_read_fifo()
272 /* Set 32MHz clock to be controlled by internal state machine */ in adux1020_read_fifo()
678 "0.1 0.2 0.5 1 2 5 10 20 50 100 190 450 820 1400");
/linux/Documentation/devicetree/bindings/thermal/
H A Dthermal-zones.yaml307 /* Corresponds to 1400MHz in OPP table */
314 /* Corresponds to 1000MHz in OPP table */
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi.c31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp.dtsi39 sdramc: sdramc@1400 {
230 /* 25 MHz reference crystal */
H A Darmada-xp-98dx3236.dtsi103 sdramc: sdramc@1400 {
265 /* 25 MHz reference crystal */
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c73 #define MHZ(x) ((x) * 1000000UL) macro
75 #define REF_CLK_RATE_MAX MHZ(64)
76 #define REF_CLK_RATE_MIN MHZ(2)
77 #define FOUT_MAX MHZ(1250)
78 #define FOUT_MIN MHZ(40)
79 #define FVCO_DIV_FACTOR MHZ(80)
249 /* limitation: 2MHz <= Fin / N <= 8MHz */ in dphy_pll_get_configure_from_opts()
250 min_n = DIV_ROUND_UP_ULL((u64)fin, MHZ(8)); in dphy_pll_get_configure_from_opts()
251 max_n = DIV_ROUND_DOWN_ULL((u64)fin, MHZ(2)); in dphy_pll_get_configure_from_opts()
317 return (clk_get_rate(dsi->clk_cfg) / MHZ(1) - 17) * 4; in dphy_pll_get_cfgclkrange()
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv6111.c146 { 1400, 0xA200 },
621 /* Tilt correction ( 0.00016 dB/MHz ) */ in get_rf_strength()
640 .frequency_min_hz = 950 * MHz,
641 .frequency_max_hz = 2150 * MHz,
/linux/drivers/pmdomain/qcom/
H A Dcpr.c977 freq_diff /= 1000000; /* Convert to MHz */ in cpr_calculate_scaling()
1011 * max_volt_scale has units of uV/MHz while freq values in cpr_interpolate()
1132 * freq(corner_N): max frequency in MHz supported by fuse corner N in cpr_corner_init()
1133 * freq(corner_N-1): max frequency in MHz supported by fuse corner in cpr_corner_init()
1142 * freq_max: max frequency in MHz supported by the fuse corner in cpr_corner_init()
1143 * freq_corner: frequency in MHz corresponding to the corner in cpr_corner_init()
1372 .max_quot_scale = 1400,
1385 .max_quot_scale = 1400,
/linux/drivers/regulator/
H A Daxp20x-regulator.c660 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
835 AXP_DESC(AXP717, CPUSLDO, "cpusldo", "vin1", 500, 1400, 50,
1072 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
1294 AXP_DESC(AXP15060, CPUSLDO, "cpusldo", NULL, 700, 1400, 50,
1346 /* The DCDC PWM frequency seems to be fixed to 3 MHz. */ in axp20x_set_dcdc_freq()
1349 "DCDC frequency on this PMIC is fixed to 3 MHz.\n"); in axp20x_set_dcdc_freq()
/linux/drivers/phy/cadence/
H A Dcdns-dphy.c116 870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500
347 * 1MHz clk (or something close). in cdns_dphy_configure()
/linux/arch/powerpc/crypto/
H A Daes-spe-glue.c33 * included. Even with the low end model clocked at 667 MHz this equals to a
35 * process a 512 byte disk block in one or a large 1400 bytes IPsec network
/linux/drivers/gpu/drm/rockchip/
H A Ddw-mipi-dsi-rockchip.c314 /* The table is based on 27MHz DPHY pll reference clock. */
422 * 000 - between 80 and 200 MHz in dw_mipi_dsi_phy_init()
423 * 001 - between 200 and 300 MHz in dw_mipi_dsi_phy_init()
424 * 010 - between 300 and 500 MHz in dw_mipi_dsi_phy_init()
425 * 011 - between 500 and 700 MHz in dw_mipi_dsi_phy_init()
426 * 100 - between 700 and 900 MHz in dw_mipi_dsi_phy_init()
427 * 101 - between 900 and 1100 MHz in dw_mipi_dsi_phy_init()
428 * 110 - between 1100 and 1300 MHz in dw_mipi_dsi_phy_init()
429 * 111 - between 1300 and 1500 MHz in dw_mipi_dsi_phy_init()
600 /* constraint: 5Mhz <= Fref / N <= 40MHz */ in dw_mipi_dsi_get_lane_mbps()
[all …]

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