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/linux/Documentation/devicetree/bindings/net/wireless/
H A Dmediatek,mt76.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Felix Fietkau <nbd@nbd.name>
12 - Lorenzo Bianconi <lorenzo@kernel.org>
13 - Ryder Lee <ryder.lee@mediatek.com>
25 - mediatek,mt76
26 - mediatek,mt7628-wmac
27 - mediatek,mt7622-wmac
[all …]
/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
82 # define SSI_NOTEMPTY(channel) (1 << (channel)) argument
[all …]
/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_rf_uw2453.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
55 RF_CHANNEL(14) = 0x4f,
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dbrcmu_d11.h1 // SPDX-License-Identifier: ISC
13 /* A chanspec (channel specification) holds the channel number, band,
20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
34 * bit 14~15 not used
54 * bit 14~15 spectral band
82 #define BRCMU_CHSPEC_D11AC_BND_SHIFT 14
100 BRCMU_CHAN_SB_NONE = -1,
118 * struct brcmu_chan - stores channel formats
121 * channel info and the other way.
[all …]
/linux/drivers/iio/adc/
H A Dtwl6030-gpadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2013 Texas Instruments Inc.
13 * Based on twl4030-madc.c
74 * struct twl6030_chnl_calib - channel calibration
86 * struct twl6030_ideal_code - GPADC calibration parameters
90 * @channel: channel number
97 int channel; member
107 * struct twl6030_gpadc_platform_data - platform specific data
112 * @channel_to_reg: pointer to ADC function to convert channel to
120 int (*start_conversion)(int channel);
[all …]
/linux/drivers/net/wireless/atmel/
H A Dat76c50x-usb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Although the code was completely re-written,
89 u8 cr39_values[14];
90 u8 reserved1[14];
91 u8 bb_cr[14];
95 u8 reserved2[14];
96 u8 cr15_values[14];
101 u8 cr20_values[14];
102 u8 cr21_values[14];
103 u8 bb_cr[14];
[all …]
/linux/drivers/clk/bcm/
H A Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
49 .channel = BCM_SR_GENPLL0_125M_CLK,
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
61 .channel = BCM_SR_GENPLL0_250M_CLK,
63 .enable = ENABLE_VAL(0x4, 8, 2, 14),
67 .channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
73 .channel = BCM_SR_GENPLL0_PAXC_AXI_X2_CLK,
[all …]
H A Dclk-ns2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
49 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
55 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
61 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
63 .enable = ENABLE_VAL(0x0, 20, 14, 0),
67 .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
73 .channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
[all …]
/linux/drivers/iio/dac/
H A Dad5446.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 * struct ad5446_state - driver instance specific data
53 * struct ad5446_chip_info - chip specific information
54 * @channel: channel spec for the DAC
60 struct iio_chan_spec channel; member
74 st->pwr_down_mode = mode + 1; in ad5446_set_powerdown_mode()
84 return st->pwr_down_mode - 1; in ad5446_get_powerdown_mode()
101 return sysfs_emit(buf, "%d\n", st->pwr_down); in ad5446_read_dac_powerdown()
119 mutex_lock(&st->lock); in ad5446_write_dac_powerdown()
120 st->pwr_down = powerdown; in ad5446_write_dac_powerdown()
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dmain.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
14 driver Copyright(c) 2003 - 2004 Intel Corporation.
31 /* Lightweight function to convert a frequency (in Mhz) to a channel number. */
35 u8 channel; in b43legacy_freq_to_channel_bg() local
38 channel = 14; in b43legacy_freq_to_channel_bg()
40 channel = (freq - 2407) / 5; in b43legacy_freq_to_channel_bg()
42 return channel; in b43legacy_freq_to_channel_bg()
51 /* Lightweight function to convert a channel number to a frequency (in Mhz). */
53 int b43legacy_channel_to_freq_bg(u8 channel) in b43legacy_channel_to_freq_bg() argument
[all …]
/linux/drivers/media/radio/si470x/
H A Dradio-si470x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/media/radio/si470x/radio-si470x.h
12 #define DRIVER_NAME "radio-si470x"
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-device.h>
51 #define POWERCFG_DMUTE 0x4000 /* bits 14..14: Mute Disable */
60 #define CHANNEL 3 /* Channel */ macro
[all …]
/linux/drivers/comedi/drivers/
H A Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
102 #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
137 /* Big Endian Byte Lane Mode - use most significant byte lanes */
[all …]
H A Dni_at_ao.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for NI AT-AO-6/10 boards
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: National Instruments AT-AO-6/10
13 * Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
19 * [0] - I/O port base address
20 * [1] - IRQ (unused)
21 * [2] - DMA (unused)
22 * [3] - analog output range, set by jumpers on hardware
23 * 0 for -10 to 10V bipolar
[all …]
/linux/tools/testing/kunit/test_data/
H A Dtest_is_test_passed-no_tests_run_no_header.log2 soft - 0
3 hard - NONE
7 Adding 24743936 bytes to physical memory to account for exec-shield gap
8 …ion 4.12.0-rc3-00010-g7319eb35f493-dirty (brendanhiggins@mactruck.svl.corp.google.com) (gcc versio…
11 PID hash table entries: 256 (order: -1, 2048 bytes)
13 Inode-cache hash table entries: 4096 (order: 3, 32768 bytes)
14 …(1681K kernel code, 480K rwdata, 400K rodata, 89K init, 205K bss, 29064K reserved, 0K cma-reserved)
15 SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
20 Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
21 Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[all …]
H A Dtest_output_isolated_correctly.log1 Linux version 5.1.0-rc7-00061-g04652f1cb4aa0 (brendanhiggins@mactruck.svl.corp.google.com) (gcc ver…
5 Inode-cache hash table entries: 32768 (order: 6, 262144 bytes)
6 …(1734K kernel code, 489K rwdata, 396K rodata, 85K init, 216K bss, 29032K reserved, 0K cma-reserved)
7 SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
10 ------------[ cut here ]------------
12 posix-timer cpumask == cpu_all_mask, using cpu_possible_mask instead
13 CPU: 0 PID: 0 Comm: swapper Not tainted 5.1.0-rc7-00061-g04652f1cb4aa0 #163
42 ---[ end trace c83434852b3702d3 ]---
45 Mount-cache hash table entries: 1024 (order: 1, 8192 bytes)
46 Mountpoint-cache hash table entries: 1024 (order: 1, 8192 bytes)
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4_dma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2007-2015 STMicroelectronics Ltd
13 /* Define the max channel number used for tx (also rx).
39 #define DMA_BUS_MODE_MB BIT(14)
70 #define DMA_SYS_BUS_MB BIT(14)
95 /* Following DMA defines are channel-oriented */
105 addr = addrs->dma_chan + (x * addrs->dma_chan_offset); in dma_chanx_base_addr()
140 /* DMA Tx Channel X Control register defines */
146 /* DMA Rx Channel X Control register defines */
148 #define DMA_RBSZ_MASK GENMASK(14, 1)
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822be_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8822bu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8822bs_efuse_parsing()
43 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_read_efuse()
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); in rtw8822b_read_efuse()
50 efuse->rfe_option = map->rfe_option; in rtw8822b_read_efuse()
51 efuse->rf_board_option = map->rf_board_option; in rtw8822b_read_efuse()
52 efuse->crystal_cap = map->xtal_k; in rtw8822b_read_efuse()
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
32 10: Multi-Channel Display Engine MCDE RX
36 14: Multirate Serial Port MSP2
[all …]
/linux/sound/usb/caiaq/
H A Dcontrol.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 struct snd_usb_caiaqdev *cdev = caiaqdev(chip->card); in control_info()
25 int pos = kcontrol->private_value; in control_info()
29 uinfo->count = 1; in control_info()
32 switch (cdev->chip.usb_id) { in control_info()
37 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in control_info()
38 uinfo->value.integer.min = 0; in control_info()
39 uinfo->value.integer.max = 2; in control_info()
54 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in control_info()
55 uinfo->value.integer.min = 0; in control_info()
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
50 #define HW_CFG_D3_VAUX_OVR_ BIT(14)
152 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
153 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
154 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
157 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
158 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
159 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
231 #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14)
248 #define MAC_WK_SRC_EEE_TX_WK_ BIT(14)
[all …]
/linux/drivers/staging/rtl8723bs/include/
H A Drtw_rf.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
25 * We now define the following channels as the max channels in each channel plan.
26 * 2G, total 14 chnls
27 * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}
29 #define MAX_CHANNEL_NUM_2G 14
30 #define MAX_CHANNEL_NUM 14
59 cQos = 0x0200, /* For HCCA, use with CF-Pollable and CF-PollReq */
79 /* Represent Channel Width in HT Capabilities */
85 /* Represent Extension Channel Offset in HT Capabilities */
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
[all …]
/linux/drivers/net/ethernet/synopsys/
H A Ddwc-xlgmac-reg.h5 * This program is dual-licensed; you may select either version 2 of
80 #define MAC_HWF0R_TXCOESEL_POS 14
84 #define MAC_HWF1R_ADDR64_POS 14
314 #define MMC_RISR_RX512TO1023OCTETS_GB_POS 14
362 #define MMC_TISR_TXOCTETCOUNT_G_POS 14
402 #define MTL_Q_RQDR_PRXQ_LEN 14
532 /* DMA channel register offsets
533 * Multiple channels can be active. The first channel has registers
534 * that begin at 0x3100. Each subsequent channel has registers that
535 * are accessed using an offset of 0x80 from the previous channel.
[all …]
/linux/arch/arm/mach-sa1100/include/mach/
H A Dirqs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/arm/mach-sa1100/include/mach/irqs.h
9 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs.
25 #define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */
32 #define IRQ_DMA0 21 /* DMA controller channel 0 */
33 #define IRQ_DMA1 22 /* DMA controller channel 1 */
34 #define IRQ_DMA2 23 /* DMA controller channel 2 */
35 #define IRQ_DMA3 24 /* DMA controller channel 3 */
36 #define IRQ_DMA4 25 /* DMA controller channel 4 */
37 #define IRQ_DMA5 26 /* DMA controller channel 5 */
[all …]
/linux/drivers/gpu/drm/tegra/
H A Dgr3d.c1 // SPDX-License-Identifier: GPL-2.0-only
42 struct host1x_channel *channel; member
62 struct drm_device *dev = dev_get_drvdata(client->host); in gr3d_init()
67 gr3d->channel = host1x_channel_request(client); in gr3d_init()
68 if (!gr3d->channel) in gr3d_init()
69 return -ENOMEM; in gr3d_init()
71 client->syncpts[0] = host1x_syncpt_request(client, flags); in gr3d_init()
72 if (!client->syncpts[0]) { in gr3d_init()
73 err = -ENOMEM; in gr3d_init()
74 dev_err(client->dev, "failed to request syncpoint: %d\n", err); in gr3d_init()
[all …]

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