Searched +full:12 +full:vdc (Results 1 – 7 of 7) sorted by relevance
| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | qrb2210-rb1.dts | 127 vdc_12v: regulator-vdc-12v {
137 vdc_1v2: regulator-vdc-1v2 {
148 vdc_3v3: regulator-vdc-3v3 {
159 vdc_5v: regulator-vdc-5v {
170 vdc_vbat_som: regulator-vdc-vbat {
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| H A D | qrb4210-rb2.dts | 176 vdc_12v: regulator-vdc-12v {
186 vdc_1v2: regulator-vdc-1v2 {
197 vdc_3v3: regulator-vdc-3v3 {
208 vdc_5v: regulator-vdc-5v {
219 vdc_vbat_som: regulator-vdc-vbat {
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| H A D | sdm845-db845c.dts | 160 gpio = <&pm8998_gpios 12 GPIO_ACTIVE_HIGH>;
244 vdc_3v3: vdc-3v3-regulator {
253 vdc_5v: vdc-5v-regulator {
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| /linux/arch/sh/kernel/cpu/sh2a/ |
| H A D | clock-sh7264.c | 24 static const unsigned int pll1rate[] = {8, 12};
63 static int div2[] = { 1, 2, 3, 4, 6, 8, 12 };
94 [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | psb_drv.h | 78 #define PSB_PTE_SHIFT 12
86 /* VDC registers and bits */
135 #define GPIO_DATA_VAL_IN (1 << 12)
411 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
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| /linux/drivers/comedi/drivers/ |
| H A D | mpc624.c | 15 * Updated: Thu, 15 Sep 2005 12:01:18 +0200
210 * We always write 0 to GNSWA bit, so the channel range is +-/10.1Vdc in mpc624_ai_insn_read()
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| /linux/drivers/pinctrl/renesas/ |
| H A D | pfc-sh7269.c | 746 /* VDC */
2098 GROUP(-12, 4),
2100 /* RESERVED [12] */
2300 GROUP(-12, 4),
2302 /* RESERVED [12] */
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