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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfaraday,ftpci100.txt30 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
50 The plain variant has 128MiB of non-prefetchable memory space, whereas the
51 "dual" variant has 64MiB. Take this into account when describing the ranges.
97 ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
99 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
104 /* 128MiB at 0x00000000-0x07ffffff */
106 /* 64MiB at 0x00000000-0x03ffffff */
108 /* 64MiB at 0x00000000-0x03ffffff */
H A Dfaraday,ftpci100.yaml21 The plain variant has 128MiB of non-prefetchable memory space, whereas the
22 "dual" variant has 64MiB. Take this into account when describing the ranges.
85 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
135 ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
137 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
142 /* 128MiB at 0x00000000-0x07ffffff */
144 /* 64MiB at 0x00000000-0x03ffffff */
146 /* 64MiB at 0x00000000-0x03ffffff */
/freebsd/sys/contrib/device-tree/Bindings/mips/
H A Dralink.txt25 This board is based on the MediaTek MT7688 and equipped with 128 MiB
26 of DDR and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND
/freebsd/sys/dev/bfe/
H A Dif_bfereg.h158 #define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
188 #define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */
192 #define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */
193 #define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */
194 #define BFE_TX_O 0x00000508 /* MIB TX Octets */
195 #define BFE_TX_P 0x0000050C /* MIB TX Packets */
196 #define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */
197 #define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */
198 #define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */
199 #define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */
[all …]
H A Dif_bfe.c833 u_int8_t eeprom[128]; in bfe_get_config()
1152 for(i = 0; i < 128; i += 2) in bfe_read_eeprom()
1241 uint32_t mib[BFE_MIB_CNT]; in bfe_stats_update() local
1246 val = mib; in bfe_stats_update()
1256 stats->tx_good_octets += mib[MIB_TX_GOOD_O]; in bfe_stats_update()
1257 stats->tx_good_frames += mib[MIB_TX_GOOD_P]; in bfe_stats_update()
1258 stats->tx_octets += mib[MIB_TX_O]; in bfe_stats_update()
1259 stats->tx_frames += mib[MIB_TX_P]; in bfe_stats_update()
1260 stats->tx_bcast_frames += mib[MIB_TX_BCAST]; in bfe_stats_update()
1261 stats->tx_mcast_frames += mib[MIB_TX_MCAST]; in bfe_stats_update()
[all …]
/freebsd/tools/test/stress2/lib/
H A Dresources.c52 static char lockpath[128];
53 static char dfpath[128];
107 int mib[16], n; in swap() local
110 mibsize = sizeof mib / sizeof mib[0]; in swap()
113 if (sysctlnametomib("vm.swap_info", mib, &mibsize) == -1) in swap()
117 mib[mibsize] = n; in swap()
119 if (sysctl(mib, mibsize + 1, &xsw, &size, NULL, 0) == -1) in swap()
161 char buf[128]; in getdf()
214 char buf[128]; in reservedf()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp51 const LLT s128 = LLT::scalar(128); in AArch64LegalizerInfo()
69 std::initializer_list<LLT> PackedVectorAllTypeList = {/* Begin 128bit types */ in AArch64LegalizerInfo()
72 /* End 128bit types */ in AArch64LegalizerInfo()
113 // Maximum: sN * k = 128 in AArch64LegalizerInfo()
341 // 128 bit base sizes in AArch64LegalizerInfo()
352 // 128 bit base sizes in AArch64LegalizerInfo()
435 // Maximum: sN * k = 128 in AArch64LegalizerInfo()
586 if (DstSize < 8 || DstSize >= 128 || !isPowerOf2_32(DstSize)) in AArch64LegalizerInfo()
592 // the source type is below 128 bits. We shouldn't be allowing anything in AArch64LegalizerInfo()
631 return DstTy.isVector() && SrcTy.getSizeInBits() > 128 && in AArch64LegalizerInfo()
[all …]
H A DAArch64InstructionSelector.cpp83 MIB.setMF(MF); in setupMF()
130 MachineIRBuilder &MIB) const;
132 MachineIRBuilder &MIB) const;
134 MachineIRBuilder &MIB) const;
137 MachineIRBuilder &MIB) const;
153 /// Copy lowest part of 128-bit or 64-bit vector to 64-bit or 32-bit
351 MachineIRBuilder &MIB) const;
356 MachineIRBuilder &MIB) const;
360 MachineIRBuilder &MIB) const;
367 MachineIRBuilder &MIB) const;
[all …]
H A DAArch64PostLegalizerCombiner.cpp305 /// Match a 128b store of zero and split it into two 64 bit stores, for
314 if (!ValTy.isVector() || ValTy.getSizeInBits() != 128) in matchSplitStoreZero128()
513 CSEMIRBuilder &MIB);
516 CSEMIRBuilder &MIB);
573 auto MIB = CSEMIRBuilder(MF); in runOnMachineFunction() local
574 MIB.setCSEInfo(CSEInfo); in runOnMachineFunction()
575 Changed |= optimizeConsecutiveMemOpAddressing(MF, MIB); in runOnMachineFunction()
580 SmallVectorImpl<StoreInfo> &Stores, CSEMIRBuilder &MIB) { in tryOptimizeConsecStores() argument
590 auto &TLI = *MIB.getMF().getSubtarget().getTargetLowering(); in tryOptimizeConsecStores()
597 auto &MRI = MIB.getMF().getRegInfo(); in tryOptimizeConsecStores()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385-linksys-caiman.dts75 /* 128MiB */
83 reg = <0x0000000 0x200000>; /* 2MiB */
99 reg = <0x900000 0x100000>; /* 1MiB */
106 reg = <0xa00000 0x2800000>; /* 40MiB */
111 reg = <0x1000000 0x2200000>; /* 34MiB */
117 reg = <0x3200000 0x2800000>; /* 40MiB */
122 reg = <0x3800000 0x2200000>; /* 34MiB */
126 * 38MiB, last MiB is for the BBT, not writable
141 reg = <0x280000 0x680000>; /* 6.5MiB */
H A Darmada-385-linksys-cobra.dts75 /* 128MiB */
83 reg = <0x0000000 0x200000>; /* 2MiB */
99 reg = <0x900000 0x100000>; /* 1MiB */
106 reg = <0xa00000 0x2800000>; /* 40MiB */
111 reg = <0x1000000 0x2200000>; /* 34MiB */
117 reg = <0x3200000 0x2800000>; /* 40MiB */
122 reg = <0x3800000 0x2200000>; /* 34MiB */
126 * 38MiB, last MiB is for the BBT, not writable
141 reg = <0x280000 0x680000>; /* 6.5MiB */
H A Darmada-385-linksys-shelby.dts75 /* 128MiB */
83 reg = <0x0000000 0x200000>; /* 2MiB */
99 reg = <0x900000 0x100000>; /* 1MiB */
106 reg = <0xa00000 0x2800000>; /* 40MiB */
111 reg = <0x1000000 0x2200000>; /* 34MiB */
117 reg = <0x3200000 0x2800000>; /* 40MiB */
122 reg = <0x3800000 0x2200000>; /* 34MiB */
126 * 38MiB, last MiB is for the BBT, not writable
141 reg = <0x280000 0x680000>; /* 6.5MiB */
H A Darmada-385-linksys-rango.dts83 /* AMD/Spansion S34ML02G2 256MiB, OEM Layout */
91 reg = <0x0000000 0x200000>; /* 2MiB */
97 reg = <0x200000 0x20000>; /* 128KiB */
120 reg = <0xa00000 0x5000000>; /* 80MiB */
125 reg = <0x1000000 0x4a00000>; /* 74MiB */
131 reg = <0x5a00000 0x5000000>; /* 80MiB */
136 reg = <0x6000000 0x4a00000>; /* 74MiB */
140 * 86MiB, last MiB is for the BBT, not writable
155 reg = <0x260000 0x5c0000>; /* 5.75MiB */
H A Darmada-370-dlink-dns327l.dts30 reg = <0x00000000 0x20000000>; /* 512 MiB */
277 /* 1.0 MiB */
284 /* 128 KiB */
291 /* 7 MiB */
297 /* ~ 84 MiB */
304 /* 5 MiB */
310 /* 29 MiB */
316 /* 1 MiB for BBT */
/freebsd/sys/contrib/openzfs/man/man4/
H A Dzfs.478 .It Sy dmu_object_alloc_chunk_shift Ns = Ns Sy 7 Po 128 Pc Pq uint
93 .It Sy dmu_prefetch_max Ns = Ns Sy 134217728 Ns B Po 128 MiB Pc Pq uint
193 .Sy 64 MiB
223 .It Sy l2arc_write_boost Ns = Ns Sy 33554432 Ns B Po 32 MiB Pc Pq u64
228 .It Sy l2arc_write_max Ns = Ns Sy 33554432 Ns B Po 32 MiB Pc Pq u64
247 .It Sy metaslab_aliquot Ns = Ns Sy 1048576 Ns B Po 1 MiB Pc Pq u64
258 .It Sy metaslab_force_ganging Ns = Ns Sy 16777217 Ns B Po 16 MiB + 1 B Pc Pq u64
293 .It Sy zfs_default_ibs Ns = Ns Sy 17 Po 128 KiB Pc Pq int
304 .It Sy zfs_history_output_max Ns = Ns Sy 1048576 Ns B Po 1 MiB Pc Pq u64
308 .Sy DMU_MAX_ACCESS Pq 64 MiB .
[all …]
/freebsd/usr.bin/netstat/
H A Droute.c244 int mib[7]; in p_rtable_sysctl() local
253 mib[0] = CTL_NET; in p_rtable_sysctl()
254 mib[1] = PF_ROUTE; in p_rtable_sysctl()
255 mib[2] = 0; in p_rtable_sysctl()
256 mib[3] = af; in p_rtable_sysctl()
257 mib[4] = NET_RT_DUMP; in p_rtable_sysctl()
258 mib[5] = 0; in p_rtable_sysctl()
259 mib[6] = fibnum; in p_rtable_sysctl()
260 if (sysctl(mib, nitems(mib), NULL, &needed, NULL, 0) < 0) in p_rtable_sysctl()
265 if (sysctl(mib, nitems(mib), buf, &needed, NULL, 0) < 0) in p_rtable_sysctl()
[all …]
H A Dnhgrp.c119 char buffer[128]; in print_nhgroup_entry_sysctl()
196 int mib[7]; in dump_nhgrp_sysctl() local
203 mib[0] = CTL_NET; in dump_nhgrp_sysctl()
204 mib[1] = PF_ROUTE; in dump_nhgrp_sysctl()
205 mib[2] = 0; in dump_nhgrp_sysctl()
206 mib[3] = af; in dump_nhgrp_sysctl()
207 mib[4] = NET_RT_NHGRP; in dump_nhgrp_sysctl()
208 mib[5] = 0; in dump_nhgrp_sysctl()
209 mib[6] = fibnum; in dump_nhgrp_sysctl()
210 if (sysctl(mib, nitems(mib), NULL, &needed, NULL, 0) < 0) in dump_nhgrp_sysctl()
[all …]
H A Dnhops.c144 char buf[128]; in print_addr()
239 char buffer[128]; in print_nhop_entry_sysctl()
240 char iface_name[128]; in print_nhop_entry_sysctl()
339 int mib[7]; in dump_nhops_sysctl() local
346 mib[0] = CTL_NET; in dump_nhops_sysctl()
347 mib[1] = PF_ROUTE; in dump_nhops_sysctl()
348 mib[2] = 0; in dump_nhops_sysctl()
349 mib[3] = af; in dump_nhops_sysctl()
350 mib[4] = NET_RT_NHOP; in dump_nhops_sysctl()
351 mib[5] = 0; in dump_nhops_sysctl()
[all …]
/freebsd/usr.sbin/ppp/
H A Darp.c96 char extra[128];
172 char space[128]; in arp_SetProxy()
231 int mib[6], skip; in arp_EtherAddr() local
239 mib[0] = CTL_NET; in arp_EtherAddr()
240 mib[1] = PF_ROUTE; in arp_EtherAddr()
241 mib[2] = 0; in arp_EtherAddr()
242 mib[3] = 0; in arp_EtherAddr()
243 mib[4] = NET_RT_IFLIST; in arp_EtherAddr()
244 mib[5] = 0; in arp_EtherAddr()
246 if (sysctl(mib, in arp_EtherAddr()
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/freebsd/sys/x86/pci/
H A Dpci_early_quirks.c45 #define MiB(v) ((unsigned long)(v) << 20) macro
104 return (MiB(1)); in intel_stolen_size_gen3()
106 return (MiB(4)); in intel_stolen_size_gen3()
108 return (MiB(8)); in intel_stolen_size_gen3()
110 return (MiB(16)); in intel_stolen_size_gen3()
112 return (MiB(32)); in intel_stolen_size_gen3()
114 return (MiB(48)); in intel_stolen_size_gen3()
116 return (MiB(64)); in intel_stolen_size_gen3()
118 return (MiB(128)); in intel_stolen_size_gen3()
[all...]
/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghash-ia64.pl20 # single multiplication operation in GF(2^128). "4-bit" means that it
21 # uses 256 bytes per-key table [+128 bytes shared table]. Streamed
60 # &rem_4bit[Zlo&0xf]. It works, because rem_4bit is aligned at 128
76 { .mib; (p19) xor Hhi=Hhi,rem
90 { .mib; (p18) xor Hhi=Hhi,rem
108 .align 128
127 { .mib; ld1 xi[2]=[Xi],-1 // Xi[15]
145 { .mib; xor Zhi=Zhi,Hhi };; // modulo-scheduling artefact
146 { .mib; mux1 Zlo=Zlo,\@rev };;
147 { .mib; mux1 Zhi=Zhi,\@rev };;
[all …]
/freebsd/usr.bin/uname/
H A Duname.c198 int mib[] = { (mib0), (mib1) }; \
204 if (sysctl(mib, sizeof mib / sizeof mib[0], \
268 static char buf[128]; in native_uservers()
277 static char buf[128]; in native_kernvers()
/freebsd/share/man/man4/
H A Dmd.4102 approximately 55 MiB may require building a custom kernel using
112 The default is 64 MiB.
116 Each L2 page can map 4 MiB of kernel space.
119 The default value is 32, which is sufficient to map 128 MiB.
136 Empirically, a value of 5 works well for a 200 MiB root image on
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg() local
93 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
96 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
184 static void addSaveRestoreRegs(MachineInstrBuilder &MIB, in addSaveRestoreRegs() argument
198 MIB.addReg(Reg, Flags); in addSaveRestoreRegs()
218 MachineInstrBuilder MIB; in makeFrame() local
219 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; in makeFrame()
220 MIB = BuildMI(MBB, I, DL, get(Opc)); in makeFrame()
222 addSaveRestoreRegs(MIB, CSI); in makeFrame()
224 MIB.addReg(Mips::S2); in makeFrame()
[all …]
/freebsd/contrib/ntp/ntpsnmpd/
H A Dntpv4-mib.mib4 -- Management Information Base (MIB)
19 NTPv4-MIB DEFINITIONS ::= BEGIN
22 MODULE-IDENTITY, OBJECT-TYPE , mib-2, Integer32, NOTIFICATION-TYPE,
30 FROM INET-ADDRESS-MIB -- RFC 4001
32 FROM SYSAPPL-MIB; -- RFC 2287
81 "This revision of the MIB module is published as RFC 5907."
83 ::= { mib-2 197 }
87 -- MIB contains 6 groups
110 "NTP date/time on the device, in 128-bit
290 "The current NTP date/time on the device, in 128-bit
[all …]

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