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/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
35 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
49 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
50 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
55 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
110 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
111 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
112 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
[all …]
/linux/arch/powerpc/crypto/
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
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H A Daes-gcm-p10.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 # Accelerated AES-GCM stitched implementation for ppc64le.
5 # Copyright 2022- IBM Inc. All rights reserved
22 # Hash keys = v3 - v14
29 # v31 - counter 1
32 # vs0 - vs14 for round keys
35 # This implementation uses stitched AES-GCM approach to improve overall performance.
48 # v15 - v18 - input states
49 # vs1 - vs9 - round keys
59 vcipher 17, 17, 19
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H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
15 # 2. c += d; b ^= c; b <<<= 12;
20 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 12
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
86 SAVE_GPR 17, 136, 1
119 SAVE_VSX 17, 240, 9
154 RESTORE_VSX 17, 240, 9
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/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32mp135.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
10 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH1_MII_CRS"),
24 STM32_FUNCTION(17, "ANALOG")
35 STM32_FUNCTION(12, "ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
36 STM32_FUNCTION(17, "ANALOG")
46 STM32_FUNCTION(12, "ETH1_MDIO"),
47 STM32_FUNCTION(17, "ANALOG")
59 STM32_FUNCTION(12, "ETH1_MII_COL"),
[all …]
H A Dpinctrl-stm32h743.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
24 STM32_FUNCTION(12, "ETH_MII_CRS"),
26 STM32_FUNCTION(17, "ANALOG")
39 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
42 STM32_FUNCTION(17, "ANALOG")
53 STM32_FUNCTION(12, "ETH_MDIO"),
57 STM32_FUNCTION(17, "ANALOG")
69 STM32_FUNCTION(12, "ETH_MII_COL"),
72 STM32_FUNCTION(17, "ANALOG")
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H A Dpinctrl-stm32f769.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH_MII_CRS"),
24 STM32_FUNCTION(17, "ANALOG")
35 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
38 STM32_FUNCTION(17, "ANALOG")
48 STM32_FUNCTION(12, "ETH_MDIO"),
52 STM32_FUNCTION(17, "ANALOG")
63 STM32_FUNCTION(12, "ETH_MII_COL"),
66 STM32_FUNCTION(17, "ANALOG")
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H A Dpinctrl-stm32mp157.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
10 #include "pinctrl-stm32.h"
25 STM32_FUNCTION(12, "ETH1_GMII_CRS ETH1_MII_CRS"),
27 STM32_FUNCTION(17, "ANALOG")
42 STM32_FUNCTION(12, "ETH1_GMII_RX_CLK ETH1_MII_RX_CLK ETH1_RGMII_RX_CLK ETH1_RMII_REF_CLK"),
45 STM32_FUNCTION(17, "ANALOG")
58 STM32_FUNCTION(12, "ETH1_MDIO"),
62 STM32_FUNCTION(17, "ANALOG")
74 STM32_FUNCTION(12, "ETH1_GMII_COL ETH1_MII_COL"),
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H A Dpinctrl-stm32mp257.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
10 #include "pinctrl-stm32.h"
29 STM32_FUNCTION(17, "ANALOG")
42 STM32_FUNCTION(12, "LCD_R3"),
46 STM32_FUNCTION(17, "ANALOG")
58 STM32_FUNCTION(12, "LCD_B0"),
62 STM32_FUNCTION(17, "ANALOG")
75 STM32_FUNCTION(12, "LCD_B1"),
79 STM32_FUNCTION(17, "ANALOG")
[all …]
H A Dpinctrl-stm32f746.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "pinctrl-stm32.h"
23 STM32_FUNCTION(12, "ETH_MII_CRS"),
25 STM32_FUNCTION(17, "ANALOG")
36 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
39 STM32_FUNCTION(17, "ANALOG")
49 STM32_FUNCTION(12, "ETH_MDIO"),
52 STM32_FUNCTION(17, "ANALOG")
62 STM32_FUNCTION(12, "ETH_MII_COL"),
65 STM32_FUNCTION(17, "ANALOG")
[all …]
H A Dpinctrl-stm32f429.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(12, "ETH_MII_CRS"),
24 STM32_FUNCTION(17, "ANALOG")
33 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
35 STM32_FUNCTION(17, "ANALOG")
44 STM32_FUNCTION(12, "ETH_MDIO"),
46 STM32_FUNCTION(17, "ANALOG")
56 STM32_FUNCTION(12, "ETH_MII_COL"),
59 STM32_FUNCTION(17, "ANALOG")
[all …]
H A Dpinctrl-stm32f469.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-stm32.h"
21 STM32_FUNCTION(12, "ETH_MII_CRS"),
23 STM32_FUNCTION(17, "ANALOG")
33 STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
36 STM32_FUNCTION(17, "ANALOG")
45 STM32_FUNCTION(12, "ETH_MDIO"),
48 STM32_FUNCTION(17, "ANALOG")
59 STM32_FUNCTION(12, "ETH_MII_COL"),
62 STM32_FUNCTION(17, "ANALOG")
[all …]
/linux/lib/zstd/compress/
H A Dclevels.h5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
17 /*-===== Pre-defined compression levels =====-*/
24 { /* "default" - for any srcSize > 256 KB */
26 { 19, 12, 13, 1, 6, 1, ZSTD_fast }, /* base for negative levels */
29 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
38 { 22, 22, 23, 6, 5, 32, ZSTD_lazy2 }, /* level 12 */
43 { 23, 23, 22, 5, 4, 64, ZSTD_btopt }, /* level 17 */
52 { 18, 12, 13, 1, 5, 1, ZSTD_fast }, /* base for negative levels */
56 { 18, 16, 17, 3, 5, 2, ZSTD_greedy }, /* level 4.*/
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/linux/arch/arm64/crypto/
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
37 * The SHA-512 round constants
111 ld1 {v8.2d-v11.2d}, [x0]
115 ld1 {v20.2d-v23.2d}, [x3], #64
118 0: ld1 {v12.2d-v15.2d}, [x1], #64
119 ld1 {v16.2d-v19.2d}, [x1], #64
138 // v0 ab cd -- ef gh ab
139 // v1 cd -- ef gh ab cd
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
24 /* from BPP 4 to 12 in steps of 0.5 */
25 #define RC_RANGE_QP420_8BPC_MAX_NUM_BPP 17
67 { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
90 { 12, 11, 11, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 5,
92 { 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6,
94 { 12, 12, 12, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7,
96 { 12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7,
98 { 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8,
100 { 15, 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 9,
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/linux/include/dt-bindings/memory/
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22 * modules dma-address-region larbs-ports
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
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H A Dmt8192-larb-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
18 * modules dma-address-region larbs-ports
21 * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
25 * larb3/6/8/10/12/15 is null.
93 #define M4U_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12)
112 #define M4U_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12)
131 #define M4U_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12)
136 #define M4U_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17)
185 #define M4U_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12)
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H A Dmt8195-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
20 * modules dma-address-region larbs-ports
23 * cam/mdp 8G ~ 12G the other larbs.
24 * N/A 12G ~ 16G
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
112 #define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12)
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/linux/include/soc/mscc/
H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
110 #define HSIO_PLL5G_CFG1_ROT_SPEED BIT(17)
137 #define HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE BIT(12)
156 #define HSIO_PLL5G_CFG3_ENA_TEST_OUT BIT(17)
161 #define HSIO_PLL5G_CFG3_FORCE_LO BIT(12)
186 #define HSIO_PLL5G_CFG6_POR_DEL_SEL(x) (((x) << 16) & GENMASK(17, 16))
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/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
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/linux/arch/arm/mach-davinci/
H A Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
51 MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false)
52 MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
60 MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false)
68 MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false)
76 MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false)
84 MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false)
[all …]
H A Dda850.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI DA850/OMAP-L138 chip specific setup
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
7 * Derived from: arch/arm/mach-davinci/da830.c
16 #include <linux/mfd/da8xx-cfgchip.h>
20 #include <clocksource/timer-davinci.h>
61 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
66 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
74 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
81 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
[all …]
/linux/drivers/media/platform/verisilicon/
H A Dhantro_g2_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
25 #define G2_REG_INTERRUPT_DEC_RDY_INT BIT(12)
42 #define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f)
43 #define g2_tab0_swap_old G2_DEC_REG(2, 12, 0x1f)
49 #define g2_ref_compress_bypass G2_DEC_REG(3, 17, 0x1)
53 #define g2_write_mvs_e G2_DEC_REG(3, 12, 0x1)
65 #define g2_sign_data_hide G2_DEC_REG(5, 12, 0x1)
84 #define g2_strong_smooth_e G2_DEC_REG(7, 17, 0x1)
85 #define g2_filt_offset_beta G2_DEC_REG(7, 12, 0x1f)
93 #define g2_bit_depth_c G2_DEC_REG(8, 17, 0xf)
[all …]
/linux/drivers/media/platform/chips-media/coda/
H A Dcoda-mpeg2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Coda multi-standard codec IP - MPEG-2 helper functions
26 return -EINVAL; in coda_mpeg2_profile()
42 return -EINVAL; in coda_mpeg2_level()
47 * Check if the buffer starts with the MPEG-2 sequence header (with or without
51 * 10 11 11 12 12 12 13 13 13 13 14 14 14 14 14 15
52 * 15 15 15 15 15 16 16 16 16 16 16 16 17 17 17 17
53 * 17 17 17 17 18 18 18 19 18 18 18 19 1a 1a 1a 1a
78 memcmp(buf + 12, u.extension_start, 4) == 0) in coda_mpeg2_parse_headers()
/linux/drivers/staging/media/rkvdec/
H A Drkvdec-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 * Jeffy Chen <jeffy.chen@rock-chips.com>
12 #include <media/v4l2-h264.h>
13 #include <media/v4l2-mem2mem.h>
16 #include "rkvdec-regs.h"
45 #define CONSTRAINT_SET3_FLAG PS_FIELD(12, 1)
133 /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */
134 CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15),
137 CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15),
140 CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127),
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