Home
last modified time | relevance | path

Searched +full:11 +full:- +full:7 (Results 1 – 25 of 1083) sorted by relevance

12345678910>>...44

/linux/arch/arm/mach-rpc/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0
18 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
19 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10,
20 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
21 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
22 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
23 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10,
24 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
25 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10,
26 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10,
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
65 { 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7,
[all...]
/linux/lib/crypto/powerpc/
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
87 ld 7,0(4)
91 ld 11,32(4)
93 mulld 22,7,6
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
14 # 4. c += d; b ^= c; b <<<= 7
19 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
198 vadduwm 3, 3, 7
216 vadduwm 11, 11, 15
224 vxor 7, 7, 11
[all …]
/linux/include/dt-bindings/memory/
H A Dmediatek,mt6893-memory-port.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
10 #include <dt-bindings/memory/mtk-memory-port.h>
17 * modules dma-address-region larbs-ports
19 * vcodec 4G ~ 8G larb4/5/7
20 * cam/mdp 8G ~ 12G larb9/11/13/14/16/17/18/19/20
35 #define M4U_PORT_L0_OVL_2L_RDMA3 MTK_M4U_DOM_ID(0, 7)
39 #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_DOM_ID(0, 11)
52 #define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_DOM_ID(1, 7)
56 #define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_DOM_ID(1, 11)
79 #define M4U_PORT_L4_VDEC_VLD_EXT_MDP MTK_M4U_DOM_ID(4, 7)
[all …]
H A Dmt8192-larb-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
18 * modules dma-address-region larbs-ports
20 * vcodec 4G ~ 8G larb4/5/7
21 * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
44 #define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7)
63 #define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
76 #define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7)
81 #define M4U_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0)
82 #define M4U_PORT_L7_VENC_REC MTK_M4U_ID(7, 1)
[all …]
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
22 * modules dma-address-region larbs-ports
24 * vcodec 4G ~ 8G larb4/7
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
52 /* LARB 4 -- VDEC */
60 #define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
64 #define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 11)
[all …]
/linux/drivers/clk/renesas/
H A Dr9a09g047-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
204 BUS_MSTOP(10, BIT(11))),
212 BUS_MSTOP(6, BIT(11))),
228 BUS_MSTOP(11, BIT(3))),
230 BUS_MSTOP(11, BIT(3))),
232 BUS_MSTOP(11, BIT(3))),
234 BUS_MSTOP(11, BIT(3))),
[all …]
H A Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
16 #include "rzv2h-cpg.h"
108 {7, 16},
112 {11, 24},
252 BUS_MSTOP(10, BIT(11))),
262 BUS_MSTOP(5, BIT(11))),
267 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
268 BUS_MSTOP(11, BIT(13))),
[all …]
H A Dr9a09g056-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
16 #include "rzv2h-cpg.h"
104 {7, 16},
108 {11, 24},
239 BUS_MSTOP(5, BIT(11))),
244 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
245 BUS_MSTOP(11, BIT(13))),
247 BUS_MSTOP(11, BIT(14))),
[all …]
/linux/drivers/media/pci/cobalt/
H A Dcobalt-cpld.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include "cobalt-cpld.h"
17 return cobalt_bus_read32(cobalt->bar1, ADRS(offset)); in cpld_read()
22 return cobalt_bus_write32(cobalt->bar1, ADRS(offset), val); in cpld_write()
36 …cobalt_info("CPLD HSMA Clk Osc register (read/write) - Must set wr trigger to load default values\… in cpld_info_ver3()
37 cobalt_info("\t\tRegister #7:\t0x%04x (0x0022)\n", in cpld_info_ver3()
45 cobalt_info("\t\tRegister #11:\t0x%04x (0x001e)\n", in cpld_info_ver3()
133 { 7, 7, 1 }, { 8, 4, 2 }, { 9, 9, 1 },
134 { 10, 5, 2 }, { 11, 11, 1 }, { 12, 6, 2 },
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/pinctrl-sg2042.h>
12 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
14 #include "sg2042-cpus.dtsi"
18 #address-cells = <2>;
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3506.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
9 #include <dt-bindings/reset/rockchip,rk3506-cru.h>
17 /* CRU-->SOFTRST_CON00 */
28 /* CRU-->SOFTRST_CON02 */
33 /* CRU-->SOFTRST_CON03 */
38 RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
42 /* CRU-->SOFTRST_CON04 */
46 RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
49 RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
[all …]
H A Drst-rk3576.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
29 RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
40 RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
41 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
42 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
43 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
44 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
45 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
46 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
[all …]
H A Drst-rk3588.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
31 RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
44 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11),
51 RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM
61 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
65 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11),
69 RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
79 RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
80 RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
[all …]
/linux/drivers/staging/media/ipu3/
H A Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
24 .even = { { 0, 3, 122, 7, 3, 0, 0 },
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
31 { 0, -12, 113, 7, 32, -5, 0 },
[all …]
/linux/lib/crypto/x86/
H A Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
4 * Copyright (C) 2017-2019 Samuel Neves <sneves@dei.uc.pt>. All Rights Reserved.
28 .byte 0, 2, 4, 6, 1, 3, 5, 7, 14, 8, 10, 12, 15, 9, 11, 13
29 .byte 14, 4, 9, 13, 10, 8, 15, 6, 5, 1, 0, 11, 3, 12, 2, 7
30 .byte 11, 12, 5, 15, 8, 0, 2, 13, 9, 10, 3, 7, 4, 14, 6, 1
31 .byte 7, 3, 13, 11, 9, 1, 12, 14, 15, 2, 5, 4, 8, 6, 10, 0
32 .byte 9, 5, 2, 10, 0, 7, 4, 15, 3, 14, 11, 6, 13, 1, 12, 8
33 .byte 2, 6, 0, 8, 12, 10, 11, 3, 1, 4, 7, 15, 9, 13, 5, 14
34 .byte 12, 1, 14, 4, 5, 15, 13, 10, 8, 0, 6, 9, 11, 7, 3, 2
[all …]
/linux/sound/soc/codecs/
H A Drt5616.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5616.h -- RT5616 ALSA SoC audio driver
17 /* I/O - Output */
21 /* I/O - Input */
24 /* I/O - ADC/DAC/DMIC */
28 /* Mixer - D-D */
33 /* Mixer - ADC */
38 /* Mixer - DAC */
57 /* Format - ADC/DAC */
62 /* Function - Analog */
[all …]
H A Drt5651.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
[all …]
H A Drt5670.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5670.h -- RT5670 ALSA SoC audio driver
17 /* I/O - Output */
20 /* I/O - Input */
26 /* I/O - ADC/DAC/DMIC */
34 /* Mixer - D-D */
47 /* Mixer - PDM */
56 /* Mixer - ADC */
61 /* Mixer - DAC */
77 /* Format - ADC/DAC */
[all …]
H A Drt5645.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer -
[all...]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32mp257.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 #include "pinctrl-stm32.h"
23 STM32_FUNCTION(7, "USART3_TX"),
26 STM32_FUNCTION(11, "ETH2_MII_RXD2 ETH2_RGMII_RXD2"),
39 STM32_FUNCTION(7, "USART6_CK"),
56 STM32_FUNCTION(7, "USART1_RX"),
58 STM32_FUNCTION(11, "I2C1_SDA"),
72 STM32_FUNCTION(7, "USART1_TX"),
75 STM32_FUNCTION(11, "I2C1_SCL"),
[all …]
/linux/lib/crypto/
H A Dblake2b.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
[all …]
/linux/include/dt-bindings/clock/
H A Drk3399-ddr.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
11 /* DDR3-800 (5-5-5) */
13 /* DDR3-800 (6-6-6) */
15 /* DDR3-1066 (6-6-6) */
17 /* DDR3-1066 (7-7-7) */
19 /* DDR3-1066 (8-8-8) */
21 /* DDR3-1333 (7-7-7) */
23 /* DDR3-1333 (8-8-8) */
25 /* DDR3-1333 (9-9-9) */
26 #define DDR3_1333H 7
[all …]

12345678910>>...44