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Searched +full:10 +full:gbase +full:- +full:kr (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev24 This attribute contains the 32-bit PHY Identifier as reported
34 This attribute contains the 32-bit PHY Identifier as reported
51 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
52 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
53 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
54 xaui, 10gbase-kr, unknown
70 32-bit hexadecimal number representing a bit mask of the
/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
16 #include "xgbe-common.h"
40 /* Rate-change complete wait/retry count */
43 /* CDR delay values for KR support (in usec) */
49 #define XGBE_RRC_FREQUENCY 10
167 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
168 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
175 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
176 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_memac.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
14 #include <linux/pcs-lynx.h>
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
64 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
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H A Dbnx2x_hsi.h3 * Copyright (c) 2007-2013 Broadcom Corporation
125 /* Up to 16 bytes of NULL-terminated string */
145 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
150 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
151 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
153 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
154 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
156 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
157 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
409 /* Default values: 2P-64, 4P-32 */
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/linux/drivers/net/pcs/
H A Dpcs-xpcs.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pcs/pcs-xpcs.h>
17 #include "pcs-xpcs.h"
172 for (compat = xpcs->desc->compat; compat->supported; compat++) in xpcs_find_compat()
173 if (compat->interface == interface) in xpcs_find_compat()
181 return &xpcs->pcs; in xpcs_to_phylink_pcs()
191 return -ENODEV; in xpcs_get_an_mode()
193 return compat->an_mode; in xpcs_get_an_mode()
202 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) in __xpcs_linkmode_supported()
203 if (compat->supported[i] == linkmode) in __xpcs_linkmode_supported()
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/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2_main.c1 // SPDX-License-Identifier: GPL-2.0
76 writel(data, priv->swth_base[0] + offset); in mvpp2_write()
81 return readl(priv->swth_base[0] + offset); in mvpp2_read()
86 return readl_relaxed(priv->swth_base[0] + offset); in mvpp2_read_relaxed()
91 return cpu % priv->nthreads; in mvpp2_cpu_to_thread()
96 writel(data, priv->cm3_base + offset); in mvpp2_cm3_write()
101 return readl(priv->cm3_base + offset); in mvpp2_cm3_read()
124 * - per-thread registers, where each thread has its own copy of the
140 * - global registers that must be accessed through a specific thread
141 * window, because they are related to an access to a per-thread
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