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/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
81 # Scan Frequency 50.900 kHz 100.00 Hz
94 mode "640x480-100"
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/linux/drivers/cpufreq/
H A Dlongrun.c21 * longrun_{low,high}_freq is needed for the conversion of cpufreq kHz
56 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
58 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
81 pctg_lo = pctg_hi = 100; in longrun_set_policy()
84 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
86 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
89 if (pctg_hi > 100) in longrun_set_policy()
90 pctg_hi = 100; in longrun_set_policy()
183 *low_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
188 *high_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
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H A Dgx-suspmod.c89 #define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
132 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
232 /* if this relation is closer to khz, use this. If it's equal, in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
247 * set cpu speed in khz.
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
259 new_khz = gx_validate_speed(khz, &gx_params->on_duration, in gx_set_cpuspeed()
268 /* if new khz == 100% of CPU speed, it is special case */ in gx_set_cpuspeed()
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/linux/drivers/video/fbdev/core/
H A Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
71 /* 640x480 @ 85 Hz, 43.27 kHz hsync */
75 /* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
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/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h128 uint32_t pixel_clk; /* in KHz */
160 uint32_t crystal_frequency; /* in KHz */
161 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
162 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
163 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
164 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
172 uint32_t default_display_engine_pll_frequency; /* in KHz */
173 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
174 uint32_t smu_gpu_pll_output_freq; /* in KHz */
177 uint32_t default_memory_clk; /* in KHz */
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H A Dbios_parser_types.h119 uint32_t pixel_clock; /* khz */
132 uint32_t pixel_clock; /* in KHz */
158 /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
159 * be pixel clock * deep_color_ratio (in KHz)
202 * standard used) in KHz
205 /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
223 * that becomes Target Pixel Clock (100 Hz units) */
235 * is enabled (KHz) */
/linux/drivers/comedi/drivers/
H A Ddt2811.c74 #define DT2811_OSC_BASE 1666 /* 600 kHz = 1666.6667ns */
80 * 0 1 600 kHz 0 1
81 * 1 10 60 kHz 1 10
82 * 2 2 300 kHz 2 100
83 * 3 3 200 kHz 3 1000
84 * 4 4 150 kHz 4 10000
85 * 5 5 120 kHz 5 100000
86 * 6 6 100 kHz 6 1000000
87 * 7 12 50 kHz 7 10000000
94 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000
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/linux/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/linux/drivers/devfreq/
H A Dtegra30-devfreq.c68 #define KHZ 1000 macro
70 #define KHZ_MAX (ULONG_MAX / KHZ)
94 * Threshold of activity (cycles translated to kHz) below which the
125 .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
147 .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
154 * Frequencies are in kHz.
242 do_div(val, 100); in do_percent()
254 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
348 avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold; in actmon_device_target_freq()
412 tegra->cur_freq = data->new_rate / KHZ; in tegra_actmon_clk_notify_cb()
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/linux/drivers/nvmem/
H A Dlpc18xx_eeprom.c38 /* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
109 /* Wait 100 us while the EEPROM wakes up */ in lpc18xx_eeprom_gather_write()
110 usleep_range(100, 200); in lpc18xx_eeprom_gather_write()
137 /* Wait 100 us while the EEPROM wakes up */ in lpc18xx_eeprom_read()
138 usleep_range(100, 200); in lpc18xx_eeprom_read()
/linux/drivers/gpu/drm/tests/
H A Ddrm_kunit_edid.h41 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
46 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
106 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
109 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
114 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
128 * VIC 16: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz
137 * Maximum TMDS clock: 100 MHz
139 * Checksum: 0xe4 Unused space in Extension Block: 100 bytes
208 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
211 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
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/linux/Documentation/hwmon/
H A Dlm85.rst153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
157 between 10 and 100 Hz, which can then be tuned separately.
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
266 -1 PWM always 100% (full on)
H A Dmcp3021.rst36 compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
H A Df71805f.rst85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
150 from 187.5 kHz (default) to 31 Hz. The best frequency depends on the
153 above the audible range, such as 25 kHz, may be a good choice; if this
155 not going below 1 kHz, as the fan tachometers get confused by lower
/linux/drivers/media/radio/si470x/
H A Dradio-si470x-common.c108 /* Spacing (kHz) */
109 /* 0: 200 kHz (USA, Australia) */
110 /* 1: 100 kHz (Europe, Japan) */
111 /* 2: 50 kHz */
114 MODULE_PARM_DESC(space, "Spacing: 0=200kHz 1=100kHz *2=50kHz*");
241 /* Spacing (kHz) */ in si470x_get_step()
243 /* 0: 200 kHz (USA, Australia) */ in si470x_get_step()
246 /* 1: 100 kHz (Europe, Japan) */ in si470x_get_step()
248 return 100 * 16; in si470x_get_step()
249 /* 2: 50 kHz */ in si470x_get_step()
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-reference-design-tablet.dtsi55 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table.c239 /* We need to convert from KHz units into 10KHz units */ in encoder_control_digx_v3()
285 /* We need to convert from KHz units into 10KHz units */ in encoder_control_digx_v4()
487 * We need to convert from KHz units into 20KHz units in transmitter_control_v2()
493 * We need to convert from KHz units into 10KHz units in transmitter_control_v2()
625 * We need to convert from KHz units into 20KHz units in transmitter_control_v3()
631 * We need to convert from KHz units into 10KHz units in transmitter_control_v3()
751 * We need to convert from KHz units into 20KHz units in transmitter_control_v4()
757 * We need to convert from KHz units into 10KHz units in transmitter_control_v4()
1000 /* We need to convert from 100Hz units into 10KHz units */ in set_pixel_clock_v3()
1002 cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100)); in set_pixel_clock_v3()
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/linux/sound/soc/codecs/
H A Dmax98373.c88 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
91 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
95 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
98 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
105 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
106 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
109 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
166 "333kHz", "192kHz", "64kHz", "48kHz"
/linux/sound/firewire/motu/
H A Dmotu-protocol-v1.c36 // 0x00000004: 48.0 kHz
37 // 0x00000000: 44.1 kHz
68 // 0x00000000: force to low rate (44.1/48.0 kHz).
97 // 0x00000000: 44.1 kHz
98 // 0x00000008: 48.0 kHz
99 // 0x00000010: 88.2 kHz
100 // 0x00000018: 96.0 kHz
355 // 100 msec. in switch_fetching_mode_828()
356 msleep(100); in switch_fetching_mode_828()
/linux/drivers/i2c/busses/
H A Di2c-stm32.h19 STM32_I2C_SPEED_STANDARD, /* 100 kHz */
20 STM32_I2C_SPEED_FAST, /* 400 kHz */
/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c20 #define MIN_OUTPUT_FREQ (100)
32 const u32 khz = 1000; in dphy_calc_pll_param() local
34 const unsigned long long factor = 100; in dphy_calc_pll_param()
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
219 const u32 scale = 100; in dphy_timing_config()
257 - 525 * t_byteck / 100, t_byteck) - 2; in dphy_timing_config()
260 + ((tmp >> 16) & 0xffff) - 525 * t_byteck / 100, in dphy_timing_config()
273 range[L] = 100 * scale; in dphy_timing_config()
/linux/include/linux/
H A Dclocksource.h55 * @freq_khz: Clocksource frequency in khz.
62 * 100-199: Base level usability.
173 * clocksource_khz2mult - calculates mult from khz and shift
174 * @khz: Clocksource frequency in KHz
177 * Helper functions that converts a khz counter frequency to a timsource
180 static inline u32 clocksource_khz2mult(u32 khz, u32 shift_constant) in clocksource_khz2mult() argument
182 return clocksource_freq2mult(khz, shift_constant, NSEC_PER_MSEC); in clocksource_khz2mult()
235 * clocksource_register_hz/khz
256 static inline int clocksource_register_khz(struct clocksource *cs, u32 khz) in clocksource_register_khz() argument
258 return __clocksource_register_scale(cs, 1000, khz); in clocksource_register_khz()
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dadt7475.yaml45 the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm
46 uses a logic high output for 100% duty cycle.
69 - 44444 (22 kHz)
129 /* PWMs at 22.5 kHz frequency, 50% duty*/
/linux/drivers/pwm/
H A Dpwm-sl28cpld.c14 * Let cnt[7:0] be the counter, clocked at 32kHz:
20 * | 2 | cnt[5] | cnt[4:0] | 1 kHz | 1000000 ns |
21 * | 3 | cnt[4] | cnt[3:0] | 2 kHz | 500000 ns |
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
54 #define SL28CPLD_PWM_CLK 32000 /* 32 kHz */
156 * Work around the hardware limitation. See also above. Trap 100% duty in sl28cpld_pwm_apply()
/linux/Documentation/admin-guide/pm/
H A Dcpufreq.rst245 the hardware (in KHz).
252 An average frequency (in KHz) of all CPUs belonging to a given policy,
267 can run at (in kHz).
271 can run at (in kHz).
286 (in kHz).
299 Current frequency of all of the CPUs belonging to this policy (in kHz).
330 running at (in kHz).
338 running at (in kHz).
348 It returns the last frequency requested by the governor (in kHz) or can
481 1 (or 100%), and the value of the ``cpuinfo_min_freq`` policy attribute
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