Home
last modified time | relevance | path

Searched +full:1000 +full:mhz (Results 1 – 25 of 314) sorted by relevance

12345678910>>...13

/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tmu.dtsi19 hysteresis = <1000>; /* millicelsius */
24 hysteresis = <1000>; /* millicelsius */
29 hysteresis = <1000>; /* millicelsius */
34 hysteresis = <1000>; /* millicelsius */
39 hysteresis = <1000>; /* millicelsius */
44 hysteresis = <1000>; /* millicelsius */
49 hysteresis = <1000>; /* millicelsius */
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
[all …]
/freebsd/sys/x86/cpufreq/
H A Dest.c84 /* Convert MHz and mV into IDs for passing to the MSR. */
85 #define ID16(MHz, mV, bus_clk) \ argument
86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
91 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ argument
92 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
93 #define FREQ_INFO(MHz, mV, bus_clk) \ argument
94 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
113 #define EST_TRANS_LAT 1000
116 * Frequency (MHz) and voltage (mV) settings.
132 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
[all …]
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_private.h74 FVCO_880 = 880 * 1000, /**< 880MHz */
75 FVCO_1760 = 1760 * 1000, /**< 1760MHz */
76 FVCO_1440 = 1440 * 1000, /**< 1440MHz */
77 FVCO_960 = 960 * 1000, /**< 960MHz */
H A Dbhnd_pmu_subr.c1152 /* the following table is based on 880Mhz fvco */
1205 /* the following table is based on 880Mhz fvco */
1244 /* the following table is based on 1760Mhz fvco */
1282 /* the following table is based on 1440Mhz fvco */
1474 return (xt->fref * 1000); in bhnd_pmu1_alpclk0()
1503 PMU_DEBUG(sc, "XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, in bhnd_pmu0_pllinit0()
1518 PMU_DEBUG(sc, "PLL already programmed for %d.%d MHz\n", in bhnd_pmu0_pllinit0()
1519 xt->freq / 1000, xt->freq % 1000); in bhnd_pmu0_pllinit0()
1525 "Reprogramming PLL for %d.%d MHz (was %d.%dMHz)\n", in bhnd_pmu0_pllinit0()
1526 xt->freq / 1000, xt->freq % 1000, in bhnd_pmu0_pllinit0()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dksz.txt24 125MHz instead of 25MHz.
35 speed = <1000>;
81 speed = <1000>;
119 speed = <1000>;
H A Dmicrochip,ksz.yaml48 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
130 speed = <1000>;
179 speed = <1000>;
217 speed = <1000>;
/freebsd/contrib/file/magic/scripts/
H A Dcreate_filemagic_flac14 ## 16.384 MHz Unknown audio application
16 ## 22.5792 MHz Redbook/CD
19 ## 24.576 MHz DAT/Video
29 ## DAT/video: 24.576 MHz * 1000000 / 512 = 48000Hz
30 ## Redbook/CD: 22.5792 MHz * 1000000 / 512 = 44100Hz
54 stripped_rate="$(LANG=C bc <<< "scale=5; ${samplerate} / 1000" | \
/freebsd/sys/dev/videomode/
H A Dedid.c247 printf("\tMax Dot Clock: %d MHz\n", in edid_print()
263 DIVIDE(DIVIDE(edid->edid_modes[i].dot_clock * 1000, in edid_print()
283 DIVIDE(DIVIDE(edid->edid_preferred_mode->dot_clock * 1000, in edid_print()
306 refresh = DIVIDE(DIVIDE(mode->dot_clock * 1000, in edid_search_mode()
312 edid->edid_modes[i].dot_clock * 1000, in edid_search_mode()
379 vmp->dot_clock = EDID_DET_TIMING_DOT_CLOCK(data) / 1000; in edid_det_timing()
516 int mhz; in edid_parse() local
633 mhz = (max_dotclock + 999) / 1000; in edid_parse()
636 if (mhz > edid->edid_range.er_max_clock) in edid_parse()
637 edid->edid_range.er_max_clock = mhz; in edid_parse()
[all …]
H A Dvesagtf.c296 DIVIDE(v_lines * params->margin_ppt, 1000) : 0; in vesagtf_mode_params()
339 * Finally we multiply by another 1000, to get value in picosec. in vesagtf_mode_params()
413 h_period = DIVIDE(h_period_est * v_field_est, v_field_rqd * 1000); in vesagtf_mode_params()
426 * And another rescaling back to mHz. Gotta love it. in vesagtf_mode_params()
438 * N.B. that the result here is in mHz. in vesagtf_mode_params()
460 DIVIDE(DIVIDE(h_pixels * params->margin_ppt, 1000), in vesagtf_mode_params()
482 * [IDEAL DUTY CYCLE] = [C'] - ([M']*[H PERIOD]/1000) in vesagtf_mode_params()
497 ((C_PRIME256(params) * 1000) - in vesagtf_mode_params()
536 * We calculate this in Hz rather than MHz, to get a value that in vesagtf_mode_params()
541 pixel_freq = DIVIDE(total_pixels * 1000000, DIVIDE(h_period, 1000)); in vesagtf_mode_params()
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dphy-ctxt.h20 /* and 320 MHz for EHT */
27 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
31 * 40Mhz |____|____|
32 * 80Mhz |____|____|____|____|
33 * 160Mhz |____|____|____|____|____|____|____|____|
34 * 320MHz |____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|
35 * code 1011 1010 1001 1000 0011 0010 0001 0000 0100 0101 0110 0111 1100 1101 1110 1111
145 * @sbb_bandwidth: 0 disabled, 1 - 40Mhz ... 4 - 320MHz
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dthermal-cooling-devices.yaml72 capacity-dmips-mhz = <607>;
99 polling-delay = <1000>;
114 /* Corresponds to 1000MHz in OPP table */
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-dhcom-som.dtsi121 reset-assert-us = <1000>;
122 reset-deassert-us = <1000>;
137 reset-assert-us = <1000>;
138 reset-deassert-us = <1000>;
167 reset-assert-us = <1000>;
168 reset-deassert-us = <1000>;
518 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
1079 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
1090 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
1113 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmedia5200.dts29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
77 usb@1000 {
/freebsd/sys/net80211/
H A Dieee80211_dfs.c59 #define NOL_TIMEOUT msecs_to_ticks(ieee80211_nol_timeout*1000)
64 #define CAC_TIMEOUT msecs_to_ticks(ieee80211_cac_timeout*1000)
148 "CAC timer on channel %u (%u MHz) stopped due to radar\n", in cac_timeout()
157 "CAC timer on channel %u (%u MHz) expired; " in cac_timeout()
191 "start %d second CAC timer on channel %u (%u MHz)\n", in ieee80211_dfs_cac_start()
211 "stop CAC timer on channel %u (%u MHz)\n", in ieee80211_dfs_cac_stop()
255 "(%u MHz) cleared after timeout\n", in dfs_timeout()
277 ic_printf(ic, "radar detected on channel %u (%u MHz)\n", in announce_radar()
280 ic_printf(ic, "radar detected on channel %u (%u MHz), " in announce_radar()
281 "moving to channel %u (%u MHz)\n", in announce_radar()
/freebsd/sys/contrib/device-tree/Bindings/ptp/
H A Dptp-qoriq.txt34 TimerOsc = selected reference clock MHz
36 NominalFreq = 1000 / tclk_period MHz
39 OutputClock = NominalFreq / tmr_prsc MHz
H A Dfsl,ptp.yaml90 TimerOsc = selected reference clock MHz
92 NominalFreq = 1000 / tclk_period MHz
95 OutputClock = NominalFreq / tmr_prsc MHz
/freebsd/usr.sbin/powerd/
H A Dpowerd.c669 poll_ival *= 1000;
748 "MHz\n", freqs[numfreqs - 1]);
758 "MHz\n", freqs[0]);
794 (u_int)(mjoules_used / 1000),
795 (int)mjoules_used % 1000);
826 (mwatts[i] * (poll_ival / 1000)) / 1000;
835 "changing frequency to %d MHz\n",
854 "changing frequency to %d MHz\n",
908 printf("load %3d%%, current freq %4d MHz (
[all...]
/freebsd/sys/dev/bhnd/cores/chipc/pwrctl/
H A Dbhnd_pwrctl_subr.c141 /* fixed 200MHz */ in bhnd_pwrctl_cpu_clkreg_m()
143 *fixed_hz = 200 * 1000 * 1000; in bhnd_pwrctl_cpu_clkreg_m()
148 /* fixed 200MHz */ in bhnd_pwrctl_cpu_clkreg_m()
150 *fixed_hz = 200 * 1000 * 1000; in bhnd_pwrctl_cpu_clkreg_m()
227 /* PLL types 3 and 7 use BASE2 (25Mhz) */ in bhnd_pwrctl_clock_rate()
421 /* set all Instaclk chip ILP to 1 MHz */ in bhnd_pwrctl_init()
/freebsd/sys/dev/clk/allwinner/
H A Dccu_d1.c206 28, 1000, /* lock */
219 28, 1000, /* lock */
222 /* PLL_PERIPH(4X) = 24 MHz * N / M1 / M0 */
233 28, 1000, /* lock */
236 /* PLL_PERIPH0(2X) = 24 MHz * N / M / P0 */
248 /* PLL_PERIPH0(800M) = 24 MHz * N / M / P1 */
260 /* PLL_PERIPH0(1X) = 24 MHz * N / M / P0 / 2 */
281 28, 1000, /* lock */
318 28, 1000, /* lock */
355 28, 1000, /* lock */
[all …]
/freebsd/sys/arm/mv/armada38x/
H A Darmada38x.c66 * On Armada38x TCLK can be configured to 250 MHz or 200 MHz. in get_tclk_armada38x()
97 return (hw_clockrate * 1000 * 1000); in get_cpu_freq_armada38x()
/freebsd/contrib/wpa/wpa_supplicant/
H A Ddpp_supplicant.c239 wait_time = 1000; in wpas_dpp_auth_resp_retry()
250 eloop_register_timeout(wait_time / 1000, in wpas_dpp_auth_resp_retry()
251 (wait_time % 1000) * 1000, in wpas_dpp_auth_resp_retry()
285 remaining = res.sec * 1000 + res.usec / 1000; in wpas_dpp_stop_listen_for_tx()
293 "DPP: Stop listen on %u MHz ending in %u ms to allow immediate TX on %u MHz for %u ms", in wpas_dpp_stop_listen_for_tx()
495 "DPP: Start listen on neg_freq %u MHz based on timeout for TX wait expiration", in wpas_dpp_neg_freq_timeout()
612 "DPP: Move from curr_freq %u MHz to neg_freq %u MHz for response", in wpas_dpp_tx_status()
641 diff_ms = diff.sec * 1000 + diff.usec / 1000; in wpas_dpp_reply_wait_timeout()
682 "DPP: Continue reply wait on channel %u MHz for %u ms", in wpas_dpp_reply_wait_timeout()
687 eloop_register_timeout(wait_time / 1000, (wait_time % 1000) * 1000, in wpas_dpp_reply_wait_timeout()
[all …]
/freebsd/sys/contrib/device-tree/src/mips/cavium-octeon/
H A Docteon_3xxx.dts186 speed = <1000>;
196 speed = <1000>;
362 /* 12MHz, 24MHz and 48MHz allowed */
382 /* 12MHz, 24MHz and 48MHz allowed */
/freebsd/sys/arm/allwinner/
H A Daw_thermal.c92 #define A83T_ADC_ACQUIRE_TIME 23 /* 24Mhz/(23 + 1) = 1us */
93 #define A83T_THERMAL_PER 1 /* 4096 * (1 + 1) / 24Mhz = 341 us */
96 #define A83T_TEMP_MUL 1000
100 #define A64_ADC_ACQUIRE_TIME 400 /* 4Mhz/(400 + 1) = 100 us */
101 #define A64_THERMAL_PER 24 /* 4096 * (24 + 1) / 4Mhz = 25.6 ms */
104 #define A64_TEMP_MUL 1000
112 #define H3_TEMP_MUL 1000
119 #define H5_ADC_ACQUIRE_TIME 479 /* 24Mhz/479 = 20us */
120 #define H5_THERMAL_PER 58 /* 4096 * (58 + 1) / 24Mhz = 10ms */
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8188.dtsi35 capacity-dmips-mhz = <282>;
53 capacity-dmips-mhz = <282>;
71 capacity-dmips-mhz = <282>;
89 capacity-dmips-mhz = <282>;
107 capacity-dmips-mhz = <282>;
125 capacity-dmips-mhz = <282>;
143 capacity-dmips-mhz = <1024>;
161 capacity-dmips-mhz = <1024>;
245 min-residency-us = <1000>;
425 polling-delay = <1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Drockchip-dwmac.txt1 Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
32 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
34 PHY provides the reference clock(50MHz), "output" means GMAC provides the

12345678910>>...13