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/linux/arch/sh/include/asm/
H A Dbl_bit_32.h10 "stc sr, %0\n\t" in set_bl_bit()
11 "or %2, %0\n\t" in set_bl_bit()
12 "and %3, %0\n\t" in set_bl_bit()
13 "ldc %0, sr\n\t" in set_bl_bit()
15 : "r" (0x10000000), "r" (0xffffff0f) in set_bl_bit()
25 "stc sr, %0\n\t" in clear_bl_bit()
26 "and %2, %0\n\t" in clear_bl_bit()
27 "ldc %0, sr\n\t" in clear_bl_bit()
29 : "1" (~0x10000000) in clear_bl_bit()
/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
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/linux/drivers/gpu/drm/radeon/
H A Drs690d.h32 #define R_00001E_K8_FB_LOCATION 0x00001E
33 #define R_00005F_MC_MISC_UMA_CNTL 0x00005F
34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
35 #define R_000078_MC_INDEX 0x000078
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF)
38 #define C_000078_MC_IND_ADDR 0xFFFFFE00
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1)
41 #define C_000078_MC_IND_WR_EN 0xFFFFFDFF
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H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
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H A Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
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/linux/drivers/platform/x86/
H A Dlg-laptop.c38 module_param(fw_debug, bool, 0);
41 #define LG_ADDRESS_SPACE_ID 0x8F
43 #define LG_ADDRESS_SPACE_DEBUG_FLAG_ADR 0x00
44 #define LG_ADDRESS_SPACE_FAN_MODE_ADR 0x03
46 #define LG_ADDRESS_SPACE_DTTM_FLAG_ADR 0x20
47 #define LG_ADDRESS_SPACE_CPU_TEMP_ADR 0x21
48 #define LG_ADDRESS_SPACE_CPU_TRIP_LOW_ADR 0x22
49 #define LG_ADDRESS_SPACE_CPU_TRIP_HIGH_ADR 0x23
50 #define LG_ADDRESS_SPACE_MB_TEMP_ADR 0x24
51 #define LG_ADDRESS_SPACE_MB_TRIP_LOW_ADR 0x25
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/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_init.c23 #define NETXEN_ADDR_ERROR (0xffffffff)
29 #define NETXEN_NIC_XDMA_RESET 0x8000ff
99 for (ring = 0; ring < adapter->max_rds_rings; ring++) { in netxen_release_rx_buffers()
101 for (i = 0; i < rds_ring->num_desc; ++i) { in netxen_release_rx_buffers()
122 for (i = 0; i < tx_ring->num_desc; i++) { in netxen_release_tx_buffers()
127 buffrag->dma = 0ULL; in netxen_release_tx_buffers()
135 buffrag->dma = 0ULL; in netxen_release_tx_buffers()
159 for (ring = 0; ring < adapter->max_rds_rings; ring++) { in netxen_free_sw_resources()
195 tx_ring->txq = netdev_get_tx_queue(netdev, 0); in netxen_alloc_sw_resources()
212 for (ring = 0; ring < adapter->max_rds_rings; ring++) { in netxen_alloc_sw_resources()
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