Searched +full:0 +full:xfffff400 (Results 1 – 13 of 13) sorted by relevance
62 0xffffffff 0xffc00c3b # pioA63 0xffffffff 0x7fff3ccf # pioB64 0xffffffff 0x007fffff # pioC69 Let's take the pioA on peripheral B whose value is 0xffc00c3b116 'gpio@[0-9a-f]+$':156 ranges = <0xfffff400 0xfffff400 0x600>;160 0xffffffff 0xffc00c3b /* pioA */161 0xffffffff 0x7fff3ccf /* pioB */162 0xffffffff 0x007fffff /* pioC */166 pinctrl_dbgu: dbgu-0 {[all …]
38 0xffffffff 0xffc00c3b /* pioA */39 0xffffffff 0x7fff3ccf /* pioB */40 0xffffffff 0x007fffff /* pioC */81 => 0xffc00c3b86 The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...87 PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...90 PULL_UP (1 << 0): indicate this pin needs a pull up.103 OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low)104 SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable106 DEBOUNCE_VAL (0x3fff << 17): debounce value.[all …]
73 reg = <0xfffff400 0x200>;
38 #size-cells = <0>;40 cpu@0 {43 reg = <0>;49 reg = <0x20000000 0x08000000>;55 #clock-cells = <0>;56 clock-frequency = <0>;61 #clock-cells = <0>;62 clock-frequency = <0>;68 reg = <0x00300000 0x28000>;71 ranges = <0 0x00300000 0x28000>;[all …]
44 #size-cells = <0>;46 cpu@0 {49 reg = <0>;55 reg = <0x20000000 0x04000000>;61 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;68 clock-frequency = <0>;74 reg = <0x00200000 0x4000>;77 ranges = <0 0x00200000 0x4000>;[all …]
43 #size-cells = <0>;45 cpu@0 {48 reg = <0>;54 reg = <0x20000000 0x04000000>;60 #clock-cells = <0>;61 clock-frequency = <0>;66 #clock-cells = <0>;67 clock-frequency = <0>;72 #clock-cells = <0>;79 reg = <0x00300000 0x10000>;[all …]
42 #size-cells = <0>;44 cpu@0 {47 reg = <0>;53 reg = <0x20000000 0x10000000>;59 #clock-cells = <0>;60 clock-frequency = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;72 reg = <0x00300000 0x8000>;75 ranges = <0 0x00300000 0x8000>;[all …]
41 #size-cells = <0>;43 cpu@0 {46 reg = <0>;52 reg = <0x20000000 0x04000000>;58 #clock-cells = <0>;59 clock-frequency = <0>;64 #clock-cells = <0>;65 clock-frequency = <0>;70 #clock-cells = <0>;77 reg = <0x002ff000 0x2000>;[all …]
44 #size-cells = <0>;46 cpu@0 {49 reg = <0>;55 reg = <0x20000000 0x10000000>;61 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;68 clock-frequency = <0>;73 #clock-cells = <0>;80 reg = <0x00300000 0x8000>;[all …]
37 #size-cells = <0>;39 cpu@0 {42 reg = <0>;48 reg = <0x20000000 0x10000000>;54 #clock-cells = <0>;59 #clock-cells = <0>;65 reg = <0x00300000 0x100000>;68 ranges = <0 0x00300000 0x100000>;79 #size-cells = <0>;81 reg = <0x00500000 0x100000[all …]
40 #size-cells = <0>;42 cpu@0 {45 reg = <0>;51 reg = <0x20000000 0x08000000>;57 #clock-cells = <0>;58 clock-frequency = <0>;63 #clock-cells = <0>;64 clock-frequency = <0>;70 reg = <0x00300000 0x14000>;73 ranges = <0 0x00300000 0x14000>;[all …]
46 #size-cells = <0>;48 cpu@0 {51 reg = <0>;57 reg = <0x70000000 0x10000000>;63 #clock-cells = <0>;64 clock-frequency = <0>;69 #clock-cells = <0>;70 clock-frequency = <0>;75 #clock-cells = <0>;82 reg = <0x00300000 0x10000>;[all …]
46 #size-cells = <0>;47 cpu@0 {50 reg = <0x0>;56 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;61 reg = <0x20000000 0x8000000>;67 #clock-cells = <0>;68 clock-frequency = <0>;73 #clock-cells = <0>;74 clock-frequency = <0>;79 #clock-cells = <0>;[all …]