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12

/linux/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
H A Dgt215.fuc3.h3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_dma */
6 /* 0x0004: ctx_dma_query */
7 0x00000000,
8 /* 0x0008: ctx_dma_src */
9 0x00000000,
10 /* 0x000c: ctx_dma_dst */
11 0x00000000,
12 /* 0x0010: ctx_query_address_high */
[all …]
H A Dgf100.fuc3.h3 /* 0x0000: ctx_object */
4 0x00000000,
5 /* 0x0004: ctx_query_address_high */
6 0x00000000,
7 /* 0x0008: ctx_query_address_low */
8 0x00000000,
9 /* 0x000c: ctx_query_counter */
10 0x00000000,
11 /* 0x0010: ctx_src_address_high */
12 0x00000000,
[all …]
/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/linux/arch/arm/include/asm/
H A Dcputype.h5 #define CPUID_ID 0
14 #define CPUID_EXT_PFR0 0x40
15 #define CPUID_EXT_PFR1 0x44
16 #define CPUID_EXT_DFR0 0x48
17 #define CPUID_EXT_AFR0 0x4c
18 #define CPUID_EXT_MMFR0 0x50
19 #define CPUID_EXT_MMFR1 0x54
20 #define CPUID_EXT_MMFR2 0x58
21 #define CPUID_EXT_MMFR3 0x5c
22 #define CPUID_EXT_ISAR0 0x60
[all …]
/linux/arch/arm/mm/
H A Dproc-xsc3.S57 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
67 mov \rd, #0x1f00
68 orr \rd, \rd, #0x00e0
69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
70 adds \rd, \rd, #0x40000000
72 subs \rd, \rd, #0x20
91 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
92 bic r0, r0, #0x1800 @ ...IZ...........
93 bic r0, r0, #0x0006 @ .............CA.
94 mcr p15, 0, r0, c1, c0, 0 @ disable caches
[all …]
/linux/drivers/net/usb/
H A Daqc111.h18 #define AQ_ACCESS_MAC 0x01
19 #define AQ_FLASH_PARAMETERS 0x20
20 #define AQ_PHY_POWER 0x31
21 #define AQ_WOL_CFG 0x60
22 #define AQ_PHY_OPS 0x61
43 #define SFR_GENERAL_STATUS 0x03
44 #define SFR_CHIP_STATUS 0x05
45 #define SFR_RX_CTL 0x0B
46 #define SFR_RX_CTL_TXPADCRC 0x0400
47 #define SFR_RX_CTL_IPE 0x0200
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Datmel-nand.txt38 device (always 0)
39 3rd entry: the memory region size (always 0x800000)
67 reg = <0x70000000 0x8000000>;
72 reg = <0xffffc070 0x490>,
73 <0xffffc500 0x100>;
81 reg = <0x10000000 0x10000000
82 0x40000000 0x30000000>;
83 ranges = <0x0 0x0 0x10000000 0x10000000
84 0x1 0x0 0x40000000 0x10000000
85 0x2 0x0 0x50000000 0x10000000
[all …]
/linux/arch/openrisc/kernel/
H A Dhead.S34 l.movhi gpr,0x0
41 #define UART_BASE_ADD 0x90000000
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
74 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
77 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
80 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
83 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dtpc0_cfg_masks.h23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
[all …]
/linux/drivers/fsi/
H A Dfsi-occ.c29 #define OCC_P9_SRAM_CMD_ADDR 0xFFFBE000
30 #define OCC_P9_SRAM_RSP_ADDR 0xFFFBF000
32 #define OCC_P10_SRAM_CMD_ADDR 0xFFFFD000
33 #define OCC_P10_SRAM_RSP_ADDR 0xFFFFE000
35 #define OCC_P10_SRAM_MODE 0x58 /* Normal mode, OCB channel 2 */
100 return 0; in occ_open()
107 ssize_t rc = 0; in occ_read()
158 * byte 0: command type in occ_write()
183 client->read_offset = 0; in occ_write()
202 return 0; in occ_release()
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9n12.dtsi42 #size-cells = <0>;
44 cpu@0 {
47 reg = <0>;
53 reg = <0x20000000 0x10000000>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
72 reg = <0x00300000 0x8000>;
75 ranges = <0 0x00300000 0x8000>;
[all …]
H A Dat91sam9x5.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x10000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
73 #clock-cells = <0>;
80 reg = <0x00300000 0x8000>;
[all …]
H A Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
/linux/drivers/atm/
H A Dnicstar.h40 #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */
90 #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C
91 #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6
102 #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */
103 #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */
104 #define BUF_NONE 0xffffffff /* Software only: */
135 ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16)
137 (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF)
139 #define NS_RSQE_VALID 0x80000000
140 #define NS_RSQE_NZGFC 0x00004000
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar953x_initvals.h39 {0x00000008, 0x00000000},
40 {0x00000030, 0x00020085},
41 {0x00000034, 0x00000005},
42 {0x00000040, 0x00000000},
43 {0x00000044, 0x00000000},
44 {0x00000048, 0x00000008},
45 {0x0000004c, 0x00000010},
46 {0x00000050, 0x00000000},
47 {0x00001040, 0x002ffc0f},
48 {0x00001044, 0x002ffc0f},
[all …]
/linux/drivers/iio/adc/
H A Dade9000.c28 #define ADE9000_REG_AIGAIN 0x000
29 #define ADE9000_REG_AVGAIN 0x00B
30 #define ADE9000_REG_AIRMSOS 0x00C
31 #define ADE9000_REG_AVRMSOS 0x00D
32 #define ADE9000_REG_APGAIN 0x00E
33 #define ADE9000_REG_AWATTOS 0x00F
34 #define ADE9000_REG_AVAROS 0x010
35 #define ADE9000_REG_AFVAROS 0x012
36 #define ADE9000_REG_CONFIG0 0x060
37 #define ADE9000_REG_DICOEFF 0x072
[all …]
/linux/drivers/scsi/isci/
H A Dregisters.h66 #define SCU_VIIT_ENTRY_ID_MASK (0xC0000000)
69 #define SCU_VIIT_ENTRY_FUNCTION_MASK (0x0FF00000)
72 #define SCU_VIIT_ENTRY_IPPTMODE_MASK (0x0001F800)
75 #define SCU_VIIT_ENTRY_LPVIE_MASK (0x00000F00)
78 #define SCU_VIIT_ENTRY_STATUS_MASK (0x000000FF)
79 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0)
81 #define SCU_VIIT_ENTRY_ID_INVALID (0 << SCU_VIIT_ENTRY_ID_SHIFT)
86 #define SCU_VIIT_IPPT_SSP_INITIATOR (0x01 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
87 #define SCU_VIIT_IPPT_SMP_INITIATOR (0x02 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
88 #define SCU_VIIT_IPPT_STP_INITIATOR (0x04 << SCU_VIIT_ENTRY_IPPTMODE_SHIFT)
[all …]
/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c53 #define RADEON_VERSION "0.2.0"
98 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
225 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
226 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
227 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
229 { 0, }
244 { OVR_CLR, 0 },
245 { OVR_WID_LEFT_RIGHT, 0 },
246 { OVR_WID_TOP_BOTTOM, 0 },
[all …]
/linux/drivers/usb/gadget/udc/
H A Dpxa25x_udc.c47 #define UDCCR 0x0000 /* UDC Control Register */
48 #define UDC_RES1 0x0004 /* UDC Undocumented - Reserved1 */
49 #define UDC_RES2 0x0008 /* UDC Undocumented - Reserved2 */
50 #define UDC_RES3 0x000C /* UDC Undocumented - Reserved3 */
51 #define UDCCS0 0x0010 /* UDC Endpoint 0 Control/Status Register */
52 #define UDCCS1 0x0014 /* UDC Endpoint 1 (IN) Control/Status Register */
53 #define UDCCS2 0x0018 /* UDC Endpoint 2 (OUT) Control/Status Register */
54 #define UDCCS3 0x001C /* UDC Endpoint 3 (IN) Control/Status Register */
55 #define UDCCS4 0x0020 /* UDC Endpoint 4 (OUT) Control/Status Register */
56 #define UDCCS5 0x0024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
[all …]
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_security.c22 while (pb_addr & 0xFFF) { in goya_pb_set_block()
23 WREG32(pb_addr, 0); in goya_pb_set_block()
34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, in goya_init_mme_protection_bits()
35 mmMME_SBB_POWER_ECO2 = 0xDFF64; in goya_init_mme_protection_bits()
67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]

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