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Searched +full:0 +full:xfffe0000 (Results 1 – 25 of 28) sorted by relevance

12

/freebsd/sys/powerpc/include/
H A Dbat.h76 #define BAT_PBS 0xfffe0000 /* physical block start */
77 #define BAT_W 0x00000040 /* 1 = write-through, 0 = write-back */
78 #define BAT_I 0x00000020 /* cache inhibit */
79 #define BAT_M 0x00000010 /* memory coherency enable */
80 #define BAT_G 0x00000008 /* guarded region */
82 #define BAT_PP_NONE 0x00000000 /* no access permission */
83 #define BAT_PP_RO_S 0x00000001 /* read-only (soft) */
84 #define BAT_PP_RW 0x00000002 /* read/write */
85 #define BAT_PP_RO 0x00000003 /* read-only */
88 #define BAT_EBS 0xfffe0000 /* effective block start */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9330_11.ini76 { 0x0000a2d8 , 0x7999a83a , 0x7999a83a , 0x7999a83a , 0x7999a83a },
77 { 0x0000a2dc , 0xffff2a52 , 0xffff2a52 , 0xffff2a52 , 0xffff2a52 },
78 { 0x0000a2e0 , 0xffffcc84 , 0xffffcc84 , 0xffffcc84 , 0xffffcc84 },
79 { 0x0000a2e4 , 0xfffff000 , 0xfffff000 , 0xfffff000 , 0xfffff000 },
80 { 0x0000a2e8 , 0xfffe0000 , 0xfffe0000 , 0xfffe0000 , 0xfffe0000 },
81 { 0x0000a410 , 0x000050d7 , 0x000050d7 , 0x000050d0 , 0x000050d0 },
82 { 0x0000a500 , 0x00022200 , 0x00022200 , 0x00000000 , 0x00000000 },
83 { 0x0000a504 , 0x05062002 , 0x05062002 , 0x04000002 , 0x04000002 },
84 { 0x0000a508 , 0x0c002e00 , 0x0c002e00 , 0x08000004 , 0x08000004 },
85 { 0x0000a50c , 0x11062202 , 0x11062202 , 0x0d000200 , 0x0d000200 },
[all …]
H A Dar9340.ini36 { 0x00009e18 , 0x00000000 , 0x00000000 , 0x00000000 , 0x00000000 },
38 { 0x00009e44 , 0x005c0000 , 0x005c0000 , 0x005c0000 , 0x005c0000 },
40 { 0x0000a258 , 0x02020200 , 0x02020200 , 0x02020200 , 0x02020200 },
42 { 0x0000a25c , 0x00000e0e , 0x00000e0e , 0x00000e0e , 0x00000e0e },
44 { 0x0000a28c , 0x00011111 , 0x00011111 , 0x00011111 , 0x00011111 },
46 { 0x0000a2c4 , 0x00148d18 , 0x00148d18 , 0x00148d20 , 0x00148d20 },
48 { 0x0000a2d8 , 0xf999a800 , 0xf999a800 , 0xf999a80c , 0xf999a80c },
50 { 0x0000a50c , 0x0000c00a , 0x0000c00a , 0x0000c00a , 0x0000c00a },
52 { 0x0000a538 , 0x00038e8c , 0x00038e8c , 0x00038e8c , 0x00038e8c },
54 { 0x0000a53c , 0x0003cecc , 0x0003cecc , 0x0003cecc , 0x0003cecc },
[all …]
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]
H A Dar9300reg.h34 #define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable
35 #define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable
36 #define AR_CR_RXD 0x00000020 // Receive disable
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
42 #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words
43 #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words
44 #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words
45 #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words
46 #define AR_CFG_SWRG 0x00000010 // byteswap register access data words
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
[all …]
/freebsd/sys/i386/i386/
H A Dk6_mem.c41 * 15 having the mask, the 1st bit being "write-combining" and the 0th bit
50 #define UWCCR 0xc0000085
53 addr = (reg) & 0xfffe0000; \
54 mask = ((reg) & 0x1fffc) >> 2; \
55 wc = ((reg) & 0x2) >> 1; \
56 uc = (reg) & 0x1; \
57 } while (0)
79 u_int32_t len = 0, wc, uc; in k6_mrmake()
82 if (desc->mr_base &~ 0xfffe0000) in k6_mrmake()
91 wc = (desc->mr_flags & MDF_WRITECOMBINE) ? 1 : 0; in k6_mrmake()
[all …]
/freebsd/contrib/expat/lib/
H A Dnametab.h34 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
35 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
36 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x04000000,
37 0x87FFFFFE, 0x07FFFFFE, 0x00000000, 0x00000000, 0xFF7FFFFF, 0xFF7FFFFF,
38 0xFFFFFFFF, 0x7FF3FFFF, 0xFFFFFDFE, 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
39 0xFFFFE00F, 0xFC31FFFF, 0x00FFFFFF, 0x00000000, 0xFFFF0000, 0xFFFFFFFF,
40 0xFFFFFFFF, 0xF80001FF, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
41 0x00000000, 0x00000000, 0xFFFFD740, 0xFFFFFFFB, 0x547F7FFF, 0x000FFFFD,
42 0xFFFFDFFE, 0xFFFFFFFF, 0xDFFEFFFF, 0xFFFFFFFF, 0xFFFF0003, 0xFFFFFFFF,
43 0xFFFF199F, 0x033FCFFF, 0x00000000, 0xFFFE0000, 0x027FFFFF, 0xFFFFFFFE,
[all …]
/freebsd/lib/msun/src/
H A Ds_rint.c29 4.50359962737049600000e+15, /* 0x43300000, 0x00000000 */
30 -4.50359962737049600000e+15, /* 0xC3300000, 0x00000000 */
41 j0 = ((i0>>20)&0x7ff)-0x3ff; in rint()
43 if(j0<0) { in rint()
44 if(((i0&0x7fffffff)|i1)==0) return x; in rint()
45 i1 |= (i0&0x0fffff); in rint()
46 i0 &= 0xfffe0000; in rint()
47 i0 |= ((i1|-i1)>>12)&0x80000; in rint()
52 SET_HIGH_WORD(t,(i0&0x7fffffff)|(sx<<31)); in rint()
55 i = (0x000fffff)>>j0; in rint()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos2200-g0s.dts43 #clock-cells = <0>;
50 pinctrl-0 = <&key_volup>;
56 gpios = <&gpa3 0 GPIO_ACTIVE_LOW>;
63 reg = <0x0 0x80000000 0x0 0x80000000>,
64 <0x8 0x80000000 0x1 0x7e000000>;
68 reg_dummy: regulator-0 {
79 reg = <0x0 0xf6200000 0x0 (1080 * 2340 * 4)>;
84 reg = <0x0 0xfcfff000 0x0 0x1000>;
89 reg = <0x0 0xfffe0000 0x0 0x20000>;
131 samsung,pins = "gpa3-0";
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]
/freebsd/sys/dev/tdfx/
H A Dtdfx_pci.c78 static int tdfx_count = 0;
86 { 0, 0 }
147 int rid = PCIR_BAR(0); in tdfx_attach()
166 tdfx_info->addr0 = (pci_read_config(dev, 0x10, 4) & 0xffff0000); in tdfx_attach()
168 device_printf(dev, "Base0 @ 0x%x\n", tdfx_info->addr0); in tdfx_attach()
177 tdfx_info->memrid = 0; in tdfx_attach()
182 device_printf(dev, "Mapped to: 0x%x\n", in tdfx_attach()
190 rid = 0x14; /* 2nd mem map */ in tdfx_attach()
191 tdfx_info->addr1 = (pci_read_config(dev, 0x14, 4) & 0xffff0000); in tdfx_attach()
193 device_printf(dev, "Base1 @ 0x%x\n", tdfx_info->addr1); in tdfx_attach()
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2l.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
49 reg = <0x02348400 0x100>;
59 reg = <0x02348800 0x100>;
66 reg = <0x02348000 0x100>;
110 reg = <0x02620690 0xc>;
112 #size-cells = <0>;
116 pinctrl-single,function-mask = <0x1>;
122 0x0 0x0 0xc0
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DConvertUTF.h3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
85 or <A0> in UTF-8, and values above 0x10FFFF in UTF-32. Conformant code
88 When the flag is set to lenient, characters over 0x10FFFF are converted
131 typedef unsigned char Boolean; /* 0 or 1 */
134 #define UNI_REPLACEMENT_CHAR (UTF32)0x0000FFFD
135 #define UNI_MAX_BMP (UTF32)0x0000FFFF
136 #define UNI_MAX_UTF16 (UTF32)0x0010FFFF
137 #define UNI_MAX_UTF32 (UTF32)0x7FFFFFFF
138 #define UNI_MAX_LEGAL_UTF32 (UTF32)0x0010FFFF
142 #define UNI_UTF16_BYTE_ORDER_MARK_NATIVE 0xFEFF
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91rm9200.dtsi44 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
55 reg = <0x20000000 0x04000000>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
68 clock-frequency = <0>;
74 reg = <0x00200000 0x4000>;
77 ranges = <0 0x00200000 0x4000>;
[all …]
H A Dat91sam9260.dtsi41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0>;
52 reg = <0x20000000 0x04000000>;
58 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #clock-cells = <0>;
77 reg = <0x002ff000 0x2000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a7778.dtsi26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0>;
47 ranges = <0 0 0x1c000000>;
53 reg = <0xfde00000 0x400>;
59 #size-cells = <0>;
67 reg = <0xfe438000 0x1000>,
68 <0xfe430000 0x100>;
77 reg = <0xfe78001c 4>,
78 <0xfe780010 4>,
[all …]
/freebsd/sys/dev/rtwn/rtl8821a/
H A Dr21a_priv.h34 { 0x421, 0x0f }, { 0x428, 0x0a }, { 0x429, 0x10 }, { 0x430, 0x00 },
35 { 0x431, 0x00 }, { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 },
36 { 0x435, 0x05 }, { 0x436, 0x07 }, { 0x437, 0x08 }, { 0x43c, 0x04 },
37 { 0x43d, 0x05 }, { 0x43e, 0x07 }, { 0x43f, 0x08 }, { 0x440, 0x5d },
38 { 0x441, 0x01 }, { 0x442, 0x00 }, { 0x444, 0x10 }, { 0x445, 0x00 },
39 { 0x446, 0x00 }, { 0x447, 0x00 }, { 0x448, 0x00 }, { 0x449, 0xf0 },
40 { 0x44a, 0x0f }, { 0x44b, 0x3e }, { 0x44c, 0x10 }, { 0x44d, 0x00 },
41 { 0x44e, 0x00 }, { 0x44f, 0x00 }, { 0x450, 0x00 }, { 0x451, 0xf0 },
42 { 0x452, 0x0f }, { 0x453, 0x00 }, { 0x456, 0x5e }, { 0x460, 0x66 },
43 { 0x461, 0x66 }, { 0x4c8, 0x3f }, { 0x4c9, 0xff }, { 0x4cc, 0xff },
[all …]
/freebsd/contrib/tcpdump/
H A Dutil-print.c58 enum date_flag { WITHOUT_DATE = 0, WITH_DATE = 1 };
59 enum time_flag { UTC_TIME = 0, LOCAL_TIME = 1 };
72 c ^= 0x40; /* DEL to ?, others to alpha */ in fn_print_char()
86 while (*s != '\0') { in fn_print_str()
108 * this will always be non-zero. Return 0 if truncated.
117 bytes = 0; in nd_printztn()
119 if (n == 0 || (ep != NULL && s >= ep)) { in nd_printztn()
130 bytes = 0; in nd_printztn()
138 if (c == '\0') { in nd_printztn()
160 while (n > 0 && (ep == NULL || s < ep)) { in nd_printn()
[all …]
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_priv.h34 { 0x010, 0x0c },
37 { 0x025, 0x0f }, { 0x072, 0x00 }, { 0x420, 0x80 }, { 0x428, 0x0a }, \
38 { 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x00 }, { 0x432, 0x00 }, \
39 { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, { 0x436, 0x07 }, \
40 { 0x437, 0x08 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x07 }, \
41 { 0x43f, 0x08 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 }, \
42 { 0x444, 0x10 }, { 0x445, 0x00 }, { 0x446, 0x00 }, { 0x447, 0x00 }, \
43 { 0x448, 0x00 }, { 0x449, 0xf0 }, { 0x44a, 0x0f }, { 0x44b, 0x3e }, \
44 { 0x44c, 0x10 }, { 0x44d, 0x00 }, { 0x44e, 0x00 }, { 0x44f, 0x00 }, \
45 { 0x450, 0x00 }, { 0x451, 0xf0 }, { 0x452, 0x0f }, { 0x453, 0x00 }, \
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie_w_reg.h51 /* [0x0] */
53 /* [0x4] */
55 /* [0x8] */
58 /* [0x10] */
63 /* [0x0] */
65 /* [0x4] */
67 /* [0x8] */
70 /* [0x10] */
72 /* [0x14] */
74 /* [0x18] */
[all …]
/freebsd/sys/dev/ispfw/
H A Dasm_2700.h38 0x0501f06c, 0x00122000, 0x00100000, 0x00014f80,
39 0x00000009, 0x0000000c, 0x00000000, 0x785ad0d5,
40 0x00000040, 0x0000f206, 0x20434f50, 0x59524947,
41 0x48542032, 0x30323220, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32377878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020392e, 0x31322e30,
45 0x30202024, 0x00000000, 0x0000002f, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00100000,
47 0x00100000, 0x00014f80, 0xffffffff, 0x00122004,
[all …]

12