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/linux/Documentation/devicetree/bindings/ufs/
H A Dhisilicon,ufs.yaml77 reg = <0x0 0xff3c0000 0x0 0x1000>,
78 <0x0 0xff3e0000 0x0 0x1000>;
84 freq-table-hz = <0 0>,
85 <0 0>;
87 resets = <&crg_rst 0x84 12>;
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3670.dtsi25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
68 reg = <0x0 0x1>;
75 reg = <0x0 0x2>;
82 reg = <0x0 0x3>;
89 reg = <0x0 0x100>;
96 reg = <0x0 0x101>;
103 reg = <0x0 0x102>;
110 reg = <0x0 0x103>;
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi36 #size-cells = <0>;
41 reg = <0xf00>;
49 reg = <0xf01>;
57 reg = <0xf02>;
65 reg = <0xf03>;
103 #clock-cells = <0>;
108 reg = <0xfe000000 0x20000>;
113 reg = <0xfe020000 0x1000>;
123 reg = <0xfe860000 0x20>;
128 reg = <0xfe860080 0x20>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-base.dtsi51 #size-cells = <0>;
79 cpu_l0: cpu@0 {
82 reg = <0x0 0x0>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x1>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
120 reg = <0x0 0x2>;
127 i-cache-size = <0x8000>;
[all …]