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/linux/Documentation/devicetree/bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml48 - "smc" : SMC #0, following the SMCCC
49 - "hvc" : HVC #0, following the SMCCC
80 '^mailbox@[0-9a-f]+$':
107 It contains tx(0) or rx(1) channel IPI id number.
190 #address-cells = <0x2>;
191 #size-cells = <0x2>;
195 xlnx,ipi-id = <0>;
202 reg = <0x0 0xff9905c0 0x0 0x20>,
203 <0x0 0xff9905e0 0x0 0x20>,
204 <0x0 0xff990e80 0x0 0x20>,
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0 0x0>;
50 i-cache-size = <0x8000>;
53 d-cache-size = <0x8000>;
62 reg = <0x0 0x1>;
69 i-cache-size = <0x8000>;
72 d-cache-size = <0x8000>;
81 reg = <0x0 0x2>;
88 i-cache-size = <0x8000>;
[all …]
H A Dpx30.dtsi39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
68 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
95 arm,psci-suspend-param = <0x0010000>;
104 arm,psci-suspend-param = <0x1010000>;
112 cpu0_opp_table: opp-table-0 {
163 #clock-cells = <0>;
[all …]
H A Drk3399-base.dtsi51 #size-cells = <0>;
79 cpu_l0: cpu@0 {
82 reg = <0x0 0x0>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x1>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
120 reg = <0x0 0x2>;
127 i-cache-size = <0x8000>;
[all …]