Searched +full:0 +full:xff060000 (Results 1 – 5 of 5) sorted by relevance
125 reg = <0xe0008000 0x1000>;130 tx-fifo-depth = <0x40>;131 rx-fifo-depth = <0x40>;137 reg = <0x40000000 0x10000>;138 clocks = <&clkc 0>, <&clkc 1>;142 tx-fifo-depth = <0x40>;143 rx-fifo-depth = <0x40>;150 reg = <0x40000000 0x2000>;151 clocks = <&clkc 0>, <&clkc 1>;155 tx-mailbox-count = <0x20>;[all …]
29 #define TRCM_TXRX 0103 * Returns success (0) or negative errno.107 int ret = 0; in i2s_tdm_prepare_enable_mclk()116 return 0; in i2s_tdm_prepare_enable_mclk()133 return 0; in i2s_tdm_runtime_suspend()156 return 0; in i2s_tdm_runtime_resume()173 * when clk_trcm > 0.214 unsigned int xfer_mask = 0; in rockchip_snd_xfer_clear()215 unsigned int xfer_val = 0; in rockchip_snd_xfer_clear()281 /* only used when clk_trcm > 0 */[all …]
44 #size-cells = <0>;46 cpu0: cpu@0 {49 reg = <0x0 0x0>;62 reg = <0x0 0x1>;72 reg = <0x0 0x2>;82 reg = <0x0 0x3>;95 arm,psci-suspend-param = <0x0010000>;109 cpu0_opp_table: opp-table-0 {149 #clock-cells = <0>;167 #clock-cells = <0>;[all …]
38 #size-cells = <0>;40 cpu0: cpu@0 {43 reg = <0x0 0x0>;50 i-cache-size = <0x8000>;53 d-cache-size = <0x8000>;62 reg = <0x0 0x1>;69 i-cache-size = <0x8000>;72 d-cache-size = <0x8000>;81 reg = <0x0 0x2>;88 i-cache-size = <0x8000>;[all …]
39 #size-cells = <0>;41 cpu0: cpu@0 {44 reg = <0x0 0x0>;56 reg = <0x0 0x1>;68 reg = <0x0 0x2>;80 reg = <0x0 0x3>;95 arm,psci-suspend-param = <0x0010000>;104 arm,psci-suspend-param = <0x1010000>;112 cpu0_opp_table: opp-table-0 {163 #clock-cells = <0>;[all …]