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/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-c3.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
27 d-cache-size = <0x8000>;
30 i-cache-size = <0x8000>;
38 reg = <0x0 0x1>;
41 d-cache-size = <0x8000>;
44 i-cache-size = <0x8000>;
53 cache-size = <0x7d000>; /* L2. 512 KB */
76 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3562.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
64 reg = <0x0 0x1>;
76 reg = <0x0 0x2>;
88 reg = <0x0 0x3>;
103 arm,psci-suspend-param = <0x0010000>;
147 opp-supported-hw = <0xf9 0xffff>;
[all …]
H A Drk3328.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0 0x0>;
50 i-cache-size = <0x8000>;
53 d-cache-size = <0x8000>;
62 reg = <0x0 0x1>;
69 i-cache-size = <0x8000>;
72 d-cache-size = <0x8000>;
81 reg = <0x0 0x2>;
88 i-cache-size = <0x8000>;
[all …]
H A Dpx30.dtsi39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
68 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
95 arm,psci-suspend-param = <0x0010000>;
104 arm,psci-suspend-param = <0x1010000>;
112 cpu0_opp_table: opp-table-0 {
163 #clock-cells = <0>;
[all …]
/linux/include/linux/
H A Dhid.h57 #define HID_ITEM_FORMAT_SHORT 0
70 #define HID_ITEM_TYPE_MAIN 0
91 #define HID_MAIN_ITEM_CONSTANT 0x001
92 #define HID_MAIN_ITEM_VARIABLE 0x002
93 #define HID_MAIN_ITEM_RELATIVE 0x004
94 #define HID_MAIN_ITEM_WRAP 0x008
95 #define HID_MAIN_ITEM_NONLINEAR 0x010
96 #define HID_MAIN_ITEM_NO_PREFERRED 0x020
97 #define HID_MAIN_ITEM_NULL_STATE 0x040
98 #define HID_MAIN_ITEM_VOLATILE 0x08
[all...]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]