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Searched +full:0 +full:xff000044 (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/hwinfo/
H A Drenesas,prr.yaml36 reg = <0xff000044 4>;
/linux/drivers/soc/renesas/
H A Drenesas-soc.c22 .reg = 0xff000044, /* PRR (Product Register) */
27 .reg = 0xff000044, /* PRR (Product Register) */
32 .reg = 0xfff00044, /* PRR (Product Register) */
41 .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
58 .reg = 0xff000044, /* PRR (Product Register) */
63 .reg = 0xfff00044, /* PRR (Product Register) */
92 .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
106 .id = 0x3b,
111 .id = 0x3f,
116 .id = 0x40,
[all …]
/linux/arch/sh/include/asm/
H A Dprocessor_32.h19 #define CCN_PVR 0xff000030
20 #define CCN_CVR 0xff000040
21 #define CCN_PRR 0xff000044
26 * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
28 #define TASK_SIZE 0x7c000000UL
48 #define SR_DSP 0x00001000
49 #define SR_IMASK 0x000000f0
50 #define SR_FD 0x00008000
51 #define SR_MD 0x40000000
53 #define SR_USER_MASK 0x00000303 // M, Q, S, T bits
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a77470.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0>;
51 L2_CA7: cache-controller-0 {
62 #clock-cells = <0>;
64 clock-frequency = <0>;
77 #clock-cells = <0>;
79 clock-frequency = <0>;
93 reg = <0 0xe6020000 0 0x0c>;
104 reg = <0 0xe6050000 0 0x50>;
[all …]