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/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-fs4.dtsi37 ranges = <0x0 0x0 0x67000000 0x00800000>;
39 crypto_mbox: crypto_mbox@0 {
41 reg = <0x00000000 0x200000>;
42 msi-parent = <&gic_its 0x4100>;
49 reg = <0x00400000 0x200000>;
51 msi-parent = <&gic_its 0x4300>;
55 raid0: raid@0 {
57 mboxes = <&raid_mbox 0 0x1 0xff00>,
58 <&raid_mbox 1 0x1 0xff00>,
59 <&raid_mbox 2 0x1 0xff00>,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
H A Dsmu_7_0_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/linux/include/linux/ssb/
H A Dssb_regs.h9 #define SSB_SDRAM_BASE 0x00000000U /* Physical SDRAM */
10 #define SSB_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
11 #define SSB_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
12 #define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
13 #define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */
14 #define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */
16 #define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
17 #define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */
19 #define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */
20 #define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */
[all …]
/linux/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
/linux/drivers/net/dsa/
H A Dlantiq_pce.h11 OUT_MAC0 = 0,
55 #define INSTR 0
61 FLAG_ITAG = 0,
89 MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
90 MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
91 MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
92 MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
93 MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
94 MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
95 MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2500usb.h20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0005
25 #define RF5222 0x0010
43 #define CSR_REG_BASE 0x0400
44 #define CSR_REG_SIZE 0x0100
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x006e
[all …]
/linux/drivers/gpu/drm/ast/
H A Dast_dram_tables.h12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
[all …]
/linux/net/smc/
H A Dsmc_ism.h18 #define SMC_EMULATED_ISM_CHID_MASK 0xFF00
19 #define SMC_ISM_IDENT_MASK 0x00FFFF
71 return rc < 0 ? rc : 0; in smc_ism_write()
76 /* CHIDs in range of 0xFF00 to 0xFFFF are reserved in __smc_ism_is_emulated()
79 * loopback-ism: 0xFFFF in __smc_ism_is_emulated()
80 * virtio-ism: 0xFF00 ~ 0xFFFE in __smc_ism_is_emulated()
82 return ((chid & 0xFF00) == 0xFF00); in __smc_ism_is_emulated()
94 return (smcd->ops->get_chid(smcd) == 0xFFFF); in smc_ism_is_loopback()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dnpc_profile.h11 #define NPC_KPU_PROFILE_VER 0x0000000100070000
12 #define NPC_KPU_VER_MAJ(ver) ((u16)(((ver) >> 32) & 0xFFFF))
13 #define NPC_KPU_VER_MIN(ver) ((u16)(((ver) >> 16) & 0xFFFF))
14 #define NPC_KPU_VER_PATCH(ver) ((u16)((ver) & 0xFFFF))
16 #define NPC_IH_W 0x8000
17 #define NPC_IH_UTAG 0x2000
19 #define NPC_ETYPE_IP 0x0800
20 #define NPC_ETYPE_IP6 0x86dd
21 #define NPC_ETYPE_ARP 0x0806
22 #define NPC_ETYPE_RARP 0x8035
[all …]
/linux/drivers/char/
H A Dtoshiba.c11 * 0xfc02: Scott Eisert <scott.e@sky-eye.com>
12 * 0xfc04: Steve VanDevender <stevev@efn.org>
13 * 0xfc08: Garth Berry <garth@itsbruce.net>
14 * 0xfc0a: Egbert Eich <eich@xfree86.org>
15 * 0xfc10: Andrew Lofthouse <Andrew.Lofthouse@robins.af.mil>
16 * 0xfc11: Spencer Olson <solson@novell.com>
17 * 0xfc13: Claudius Frankewitz <kryp@gmx.de>
18 * 0xfc15: Tom May <tom@you-bastards.com>
19 * 0xfc17: Dave Konrad <konrad@xenia.it>
20 * 0xfc1a: George Betzos <betzos@engr.colostate.edu>
[all …]
/linux/arch/arm/lib/
H A Dbswapsdi2.S21 bic r3, r3, #0xff00
32 bic r3, r3, #0xff00
33 bic r1, r1, #0xff00
/linux/drivers/net/phy/
H A Dmdio-open-alliance.h14 #define MDIO_OATC14_PLCA_IDVER 0xca00 /* PLCA ID and version */
15 #define MDIO_OATC14_PLCA_CTRL0 0xca01 /* PLCA Control register 0 */
16 #define MDIO_OATC14_PLCA_CTRL1 0xca02 /* PLCA Control register 1 */
17 #define MDIO_OATC14_PLCA_STATUS 0xca03 /* PLCA Status register */
18 #define MDIO_OATC14_PLCA_TOTMR 0xca04 /* PLCA TO Timer register */
19 #define MDIO_OATC14_PLCA_BURST 0xca05 /* PLCA BURST mode register */
22 #define MDIO_OATC14_PLCA_IDM 0xff00 /* PLCA MAP ID */
23 #define MDIO_OATC14_PLCA_VER 0x00ff /* PLCA MAP version */
30 #define MDIO_OATC14_PLCA_NCNT 0xff00 /* PLCA node count */
31 #define MDIO_OATC14_PLCA_ID 0x00ff /* PLCA local node ID */
[all …]
/linux/drivers/infiniband/hw/efa/
H A Defa_regs_defs.h10 EFA_REGS_RESET_NORMAL = 0,
24 /* 0 base */
25 #define EFA_REGS_VERSION_OFF 0x0
26 #define EFA_REGS_CONTROLLER_VERSION_OFF 0x4
27 #define EFA_REGS_CAPS_OFF 0x8
28 #define EFA_REGS_AQ_BASE_LO_OFF 0x10
29 #define EFA_REGS_AQ_BASE_HI_OFF 0x14
30 #define EFA_REGS_AQ_CAPS_OFF 0x18
31 #define EFA_REGS_ACQ_BASE_LO_OFF 0x20
32 #define EFA_REGS_ACQ_BASE_HI_OFF 0x24
[all …]
/linux/arch/arm/mach-omap2/
H A Dsdrc2xxx.c33 #define M_UNLOCK 0
67 return 0; in omap2xxx_sdrc_dll_is_unlocked()
101 writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP); in omap2xxx_sdrc_reprogram()
103 writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP); in omap2xxx_sdrc_reprogram()
115 u32 fast_dll = 0; in omap2xxx_sdrc_init_params()
117 /* DDR = 1, SDR = 0 */ in omap2xxx_sdrc_init_params()
118 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); in omap2xxx_sdrc_init_params()
126 mem_timings.base_cs = 0; in omap2xxx_sdrc_init_params()
137 if (mem_timings.base_cs == 0) { in omap2xxx_sdrc_init_params()
139 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00; in omap2xxx_sdrc_init_params()
[all …]
/linux/arch/arm/mach-omap1/
H A Dsleep.S72 mov r4, #TCMIF_ASM_BASE & 0xff000000
73 orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
74 orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
78 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
79 bic r5, r5, #PDE_BIT & 0xff
80 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
83 and r5, r5, #PWD_EN_BIT & 0xff
84 str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
87 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
88 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
[all …]
/linux/drivers/net/ethernet/amazon/ena/
H A Dena_regs_defs.h9 ENA_REGS_RESET_NORMAL = 0,
30 /* 0 base */
31 #define ENA_REGS_VERSION_OFF 0x0
32 #define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
33 #define ENA_REGS_CAPS_OFF 0x8
34 #define ENA_REGS_CAPS_EXT_OFF 0xc
35 #define ENA_REGS_AQ_BASE_LO_OFF 0x10
36 #define ENA_REGS_AQ_BASE_HI_OFF 0x14
37 #define ENA_REGS_AQ_CAPS_OFF 0x18
38 #define ENA_REGS_ACQ_BASE_LO_OFF 0x20
[all …]

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