Searched +full:0 +full:xfed80000 (Results 1 – 8 of 8) sorted by relevance
15 #define SP5100_WDT_MEM_MAP_SIZE 0x0816 #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */17 #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */19 #define SP5100_WDT_START_STOP_BIT BIT(0)25 #define SP5100_PM_IOPORTS_SIZE 0x0233 #define SP5100_IO_PM_INDEX_REG 0xCD634 #define SP5100_IO_PM_DATA_REG 0xCD737 #define SP5100_SB_RESOURCE_MMIO_BASE 0x9C39 #define SP5100_PM_WATCHDOG_CONTROL 0x6940 #define SP5100_PM_WATCHDOG_BASE 0x6C[all …]
66 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C135 reg = <0xfed80000 0x10000>;
20 #define AMD_FCH_MMIO_BASE 0xFED8000021 #define AMD_FCH_GPIO_BANK0_BASE 0x150022 #define AMD_FCH_GPIO_SIZE 0x030058 return 0; in amd_fch_gpio_direction_input()81 return 0; in amd_fch_gpio_direction_output()116 return 0; in amd_fch_gpio_set()137 return 0; in amd_fch_gpio_request()
29 #define UDPHY_PCS 0x400030 #define UDPHY_PMA 0x800038 #define DP_LANE_SEL_ALL GENMASK(7, 0)41 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */45 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)47 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */51 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */53 #define CMN_LCPLL_SSC_EN BIT(0)55 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */59 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */[all …]
21 #clock-cells = <0>;22 clock-frequency = <0>;28 #clock-cells = <0>;29 clock-frequency = <0>;32 cluster0_opp: opp-table-0 {49 #size-cells = <0>;68 a76_0: cpu@0 {70 reg = <0>;82 reg = <0x100>;94 reg = <0x200>;[all …]
21 #clock-cells = <0>;22 clock-frequency = <0>;28 #clock-cells = <0>;29 clock-frequency = <0>;32 cluster0_opp: opp-table-0 {67 #size-cells = <0>;89 a76_0: cpu@0 {91 reg = <0>;103 reg = <0x100>;115 reg = <0x10000>;[all …]
21 #clock-cells = <0>;22 clock-frequency = <0>;27 #size-cells = <0>;29 a76_0: cpu@0 {31 reg = <0>;38 L3_CA76_0: cache-controller-0 {48 #clock-cells = <0>;50 clock-frequency = <0>;56 #clock-cells = <0>;58 clock-frequency = <0>;[all …]
57 #size-cells = <0>;92 cpu_l0: cpu@0 {95 reg = <0x0>;114 reg = <0x100>;133 reg = <0x200>;152 reg = <0x300>;171 reg = <0x400>;190 reg = <0x500>;209 reg = <0x600>;228 reg = <0x700>;[all …]