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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-naneng-combphy.yaml132 reg = <0xfdc50000 0x1000>;
137 reg = <0xfdc70000 0x1000>;
142 reg = <0xfe820000 0x100>;
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi11 cpu0_opp_table: opp-table-0 {
101 reg = <0 0xfc000000 0 0x1000>;
108 ports-implemented = <0x1>;
115 reg = <0x0 0xfdc70000 0x0 0x1000>;
120 reg = <0x0 0xfe190080 0x0 0x20>;
125 reg = <0x0 0xfe190100 0x0 0x20>;
130 reg = <0x0 0xfe190200 0x0 0x20>;
135 reg = <0x0 0xfdcb8000 0x0 0x10000>;
140 reg = <0x0 0xfe8c0000 0x0 0x20000>;
141 #phy-cells = <0>;
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define RK3528_PHYREG6 0x18
26 #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
28 #define RK3528_PHYREG6_SSC_UPWARD 0
31 #define RK3528_PHYREG40 0x100
33 #define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0)
34 #define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d
36 #define RK3528_PHYREG42 0x108
38 #define RK3528_PHYREG42_CKDRV_CLK_PLL 0
41 #define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9
[all …]