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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dqoriq-fman3-0.dtsi14 cell-index = <0>;
16 ranges = <0x0 0x0 0x1a00000 0xfe000>;
17 reg = <0x0 0x1a00000 0x0 0xfe000>;
20 clocks = <&clockgen QORIQ_CLK_FMAN 0>;
22 fsl,qman-channel-range = <0x800 0x10>;
26 muram@0 {
28 reg = <0x0 0x60000>;
32 cell-index = <0x2>;
34 reg = <0x82000 0x1000>;
38 cell-index = <0x3>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dqoriq-fman3-1.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x820 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
56 reg = <0x82000 0x1000>;
60 cell-index = <0x3>;
[all …]
H A Dqoriq-fman-0.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x40 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
[all …]
H A Dqoriq-fman-1.dtsi2 * QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x60 0xc>;
48 muram@0 {
50 reg = <0x0 0x28000>;
54 cell-index = <0x1>;
56 reg = <0x81000 0x1000>;
60 cell-index = <0x2>;
[all …]
H A Dqoriq-fman3l-0.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x800 0x10>;
48 muram@0 {
50 reg = <0x0 0x30000>;
54 cell-index = <0x2>;
[all …]
H A Dqoriq-fman3-0.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
38 cell-index = <0>;
40 ranges = <0 0x400000 0xfe000>;
41 reg = <0x400000 0xfe000>;
42 interrupts = <96 2 0 0>, <16 2 1 1>;
43 clocks = <&clockgen 3 0>;
45 fsl,qman-channel-range = <0x800 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7921/
H A Dregs.h9 #define MT_MDP_BASE 0x820cd000
12 #define MT_MDP_DCR0 MT_MDP(0x000)
16 #define MT_MDP_DCR1 MT_MDP(0x004)
19 #define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
24 #define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
28 #define MT_MDP_TO_HIF 0
31 #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204)
61 #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x520)
63 #define MT_INFRA_CFG_BASE 0xfe000
66 #define MT_HIF_REMAP_L1 MT_INFRA(0x24c)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dfsl,fman.yaml22 FMan block. The offset is 0xc4 from the beginning of the
23 Frame Processing Manager memory map (0xc3000 from the
38 DEVDISR[1] 1 0
43 DCFG_DEVDISR2[6] 1 0
50 DCFG_CCSR_DEVDISR2[24] 1 0
156 reg = <0x400000 0x100000>;
157 ranges = <0 0x400000 0x100000>;
165 fsl,qman-channel-range = <0x40 0xc>;
167 muram@0 {
169 reg = <0x0 0x28000>;
[all …]
H A Dfsl-fman.txt28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
44 DEVDISR[1] 1 0
49 DCFG_DEVDISR2[6] 1 0
56 DCFG_CCSR_DEVDISR2[24] 1 0
148 muram@0 {
150 ranges = <0 0x000000 0x28000>;
215 cell-index = <0x28>;
217 reg = <0xa8000 0x1000>;
221 cell-index = <0x8>;
[all …]
/freebsd/sys/i386/i386/
H A Dgeode.c43 { 0xf0000, 0xf1000 },
45 { "Soekris", 0, 8 }, /* Soekris Engineering. */
46 { "net4", 0, 8 }, /* net45xx */
47 { "comBIOS", 0, 54 }, /* comBIOS ver. 1.26a 20040819 ... */
48 { NULL, 0, 0 },
53 { 0xf0000, 0xf1000 },
55 { "Soekris", 0, 8 }, /* Soekris Engineering. */
56 { "net5", 0, 8 }, /* net5xxx */
57 { "comBIOS", 0, 54 }, /* comBIOS ver. 1.26a 20040819 ... */
58 { NULL, 0, 0 },
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Deth_common.h65 #define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000 /* Maximum LSO packet TCP payload leng…
67 #define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF /* Value for a connection for which same…
81 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 /* CRC seed for multicast bin calculation */
102 #define ETH_GFT_TRASHCAN_VPORT 0x1FF /* GFT drop flow vport number */
131 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1 /* Set to 1 in the first BD. (for debug) */
132 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
133 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1 /* Do not allow additional VLAN manipulations…
135 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1 /* Recalculate IP checksum. For tunneled pack…
137 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1 /* Recalculate TCP/UDP checksum. For tunneled…
139 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1 /* If set, insert VLAN tag from vlan field to…
[all …]
/freebsd/sys/dts/powerpc/
H A Dp3041si.dtsi103 #size-cells = <0>;
105 cpu0: PowerPC,e500mc@0 {
107 reg = <0>;
145 dcsr-epu@0 {
147 interrupts = <52 2 0 0
148 84 2 0 0
149 85 2 0 0>;
151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
[all …]
H A Dp5020si.dtsi109 #size-cells = <0>;
111 cpu0: PowerPC,e5500@0 {
113 reg = <0>;
135 dcsr-epu@0 {
137 interrupts = <52 2 0 0
138 84 2 0 0
139 85 2 0 0>;
141 reg = <0x0 0x1000>;
145 reg = <0x1000 0x1000 0x1000000 0x8000>;
149 reg = <0x2000 0x1000>;
[all …]
/freebsd/sys/dev/bxe/
H A Dbxe_dump.h33 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
34 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
35 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
36 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
56 #define BNX2X_DUMP_VERSION 0x61111111
76 static const uint32_t page_vals_e2[] = {0, 128};
79 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
85 static const uint32_t page_vals_e3[] = {0, 128};
88 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
92 { 0x2000, 1, 0x1f, 0xfff},
[all …]