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/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_cfg.c19 .io_offset = 0,
25 { 0x4700000, 0x5800000 },
46 { 0xfd922800, 0xfd922b00 },
66 { 0x1a98000 },
77 { 0x1a94000, 0x1a96000 },
97 { 0xfd998000, 0xfd9a0000 },
114 { 0x994000, 0x996000 },
134 { 0xc994000, 0xc996000 },
153 { 0xc994000, 0xc996000 },
173 { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
[all …]
/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm.c39 #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0)
109 writel(0, base + REG_DSI_28nm_PHY_PLL_TEST_CFG); in pll_28nm_software_reset()
135 for (i = 0; i < LPFR_LUT_SIZE; i++) in dsi_pll_28nm_clk_set_rate()
146 writel(0x70, base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG); in dsi_pll_28nm_clk_set_rate()
147 writel(0x15, base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG); in dsi_pll_28nm_clk_set_rate()
156 refclk_cfg = 0x0; in dsi_pll_28nm_clk_set_rate()
157 frac_n_mode = 0; in dsi_pll_28nm_clk_set_rate()
171 rem = 0; in dsi_pll_28nm_clk_set_rate()
175 sdm_cfg0 = 0x0; in dsi_pll_28nm_clk_set_rate()
176 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); in dsi_pll_28nm_clk_set_rate()
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8226.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
40 #size-cells = <0>;
42 cpu0: cpu@0 {
46 reg = <0>;
109 memory@0 {
111 reg = <0x0 0x0>;
160 mboxes = <&apcs 0>;
212 reg = <0x3000000 0x100000>;
217 reg = <0x0dc00000 0x1900000>;
[all …]
H A Dqcom-msm8974.dtsi22 #clock-cells = <0>;
28 #clock-cells = <0>;
35 #size-cells = <0>;
38 cpu0: cpu@0 {
42 reg = <0>;
108 memory@0 {
110 reg = <0x0 0x0>;
135 mboxes = <&apcs 0>;
158 reg = <0x08000000 0x5100000>;
163 reg = <0x0d100000 0x100000>;
[all …]