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/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2701.c38 /* 0E4E8SR 4/8/12/16 */
40 /* 0E2E4SR 2/4/6/8 */
43 MTK_DRV_GRP(2, 16, 0, 2, 2)
47 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
48 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
H A Dpinctrl-mt7623.c13 #define PIN_BOND_REG0 0xb10
14 #define PIN_BOND_REG1 0xf20
15 #define PIN_BOND_REG2 0xef0
16 #define BOND_PCIE_CLR (0x77 << 3)
17 #define BOND_I2S_CLR 0x3
18 #define BOND_MSDC0E_CLR 0x1
21 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
25 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
26 _x_bits, 16, 0)
29 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
[all …]
/linux/scripts/
H A Dcheckstack.pl53 $x = "[0-9a-f]"; # hex character
54 $xs = "[0-9a-f ]"; # hex character or space
58 #a110: d11643ff sub sp, sp, #0x590
59 $re = qr/^.*stp.*sp, ?\#-([0-9]{1,8})\]\!/o;
60 $dre = qr/^.*sub.*sp, sp, #(0x$x{1,8})/o;
62 #c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64
63 $re = qr/.*sub.*sp, sp, #([0-9]{1,4})/o;
66 #c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp
68 # 2f60: 48 81 ec e8 05 00 00 sub $0x5e8,%rsp
69 $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%(e|r)sp$/o;
[all …]
/linux/drivers/watchdog/
H A Dsbsa_gwdt.c33 * if action is 0 (the single stage mode):
58 #define SBSA_GWDT_WRR 0x000
61 #define SBSA_GWDT_WCS 0x000
62 #define SBSA_GWDT_WOR 0x008
63 #define SBSA_GWDT_WCV 0x010
66 #define SBSA_GWDT_W_IIDR 0xfcc
67 #define SBSA_GWDT_IDR 0xfd0
70 #define SBSA_GWDT_WCS_EN BIT(0)
74 #define SBSA_GWDT_VERSION_MASK GENMASK(3, 0)
77 #define SBSA_GWDT_IMPL_MASK GENMASK(11, 0)
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Daiutils.c35 #define SCC_SS_MASK 0x00000007
37 #define SCC_SS_LPO 0x00000000
39 #define SCC_SS_XTAL 0x00000001
41 #define SCC_SS_PCI 0x00000002
42 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
43 #define SCC_LF 0x00000200
44 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
45 #define SCC_LP 0x00000400
46 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
47 #define SCC_FS 0x00000800
[all …]
/linux/drivers/perf/
H A Darm_smmuv3_pmu.c10 * to 4K boundary. For example, the PMCG at 0xff88840000 is named
15 * filter_enable - 0 = no filtering, 1 = filtering enabled
16 * filter_span - 0 = exact match, 1 = pattern match
22 * STREAMID[Y - 1] == 0.
23 * STREAMID[Y - 2:0] == 1 (where Y > 1).
28 * filter_span=1,filter_stream_id=0x42/ -a netperf
29 * Applies filter pattern 0x42 to transaction events, which means events
30 * matching stream ids 0x42 and 0x43 are counted. Further filtering
57 #define SMMU_PMCG_EVCNTR0 0x0
59 #define SMMU_PMCG_EVTYPER0 0x400
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/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
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