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Searched +full:0 +full:xf7800000 (Results 1 – 4 of 4) sorted by relevance

/linux/arch/sh/include/cpu-sh4/cpu/
H A Dmmu_context.h10 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
11 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
12 #define MMU_TTB 0xFF000008 /* Translation table base register */
13 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
14 #define MMU_PTEA 0xFF000034 /* PTE assistance register */
15 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
17 #define MMUCR 0xFF000010 /* MMU Control Register */
21 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
23 #define MMU_ITLB_DATA_ARRAY 0xF3000000
[all …]
/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dhi6220-domain-ctrl.yaml52 reg = <0xf7800000 0x2000>;
59 reg = <0xf4410000 0x1000>;
65 reg = <0xf7032000 0x1000>;
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8998-xiaomi-sagit.dts39 qcom,board-id = <30 0>;
48 reg = <0x0 0x8b200000 0x0 0x1e00000>;
53 reg = <0x0 0x8d000000 0x0 0x7000000>;
58 reg = <0x0 0x94000000 0x0 0x500000>;
63 reg = <0x0 0x94500000 0x0 0x200000>;
68 reg = <0x0 0x94700000 0x0 0xf00000>;
73 reg = <0x0 0x95600000 0x0 0x10000>;
78 reg = <0x0 0x95610000 0x0 0x5000>;
83 reg = <0x0 0x95615000 0x0 0x100000>;
88 reg = <0x0 0x95715000 0x0 0x100000>;
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220.dtsi27 #size-cells = <0>;
66 arm,psci-suspend-param = <0x0010000>;
75 arm,psci-suspend-param = <0x1010000>;
83 cpu0: cpu@0 {
86 reg = <0x0 0x0>;
89 clocks = <&stub_clock 0>;
99 reg = <0x0 0x1>;
102 clocks = <&stub_clock 0>;
112 reg = <0x0 0x2>;
115 clocks = <&stub_clock 0>;
[all …]