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Searched +full:0 +full:xf5000000 (Results 1 – 11 of 11) sorted by relevance

/linux/arch/arm/mach-imx/
H A Dhardware.h21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
41 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
43 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
44 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
45 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
47 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
48 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
51 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dhisilicon,kirin-pcie.yaml78 reg = <0x0 0xf4000000 0x0 0x1000>,
79 <0x0 0xff3fe000 0x0 0x1000>,
80 <0x0 0xf3f20000 0x0 0x40000>,
81 <0x0 0xf5000000 0x0 0x2000>;
83 bus-range = <0x0 0xff>;
87 ranges = <0x02000000 0x0 0x00000000
88 0x0 0xf6000000
89 0x0 0x02000000>;
92 interrupts = <0 283 4>;
94 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/linux/arch/sh/include/cpu-sh4/cpu/
H A Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
/linux/arch/arm/mach-sa1100/include/mach/
H A Dmemory.h22 * node 0: 0xc0000000 - 0xc7ffffff
23 * node 1: 0xc8000000 - 0xcfffffff
24 * node 2: 0xd0000000 - 0xd7ffffff
25 * node 3: 0xd8000000 - 0xdfffffff
33 #define FLUSH_BASE_PHYS 0xe0000000
34 #define FLUSH_BASE 0xf5000000
35 #define FLUSH_BASE_MINICACHE 0xf5100000
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/linux/arch/powerpc/platforms/pasemi/
H A Dsetup.c53 static int nmi_virq = 0;
63 out_le32(reset_reg, 0x6000000); in pas_restart()
70 void __iomem *pld_map = ioremap(0xf5000000,4096); in pas_shutdown()
72 out_8(pld_map+7,0x01); in pas_shutdown()
78 .start = 0x70,
79 .end = 0x71,
128 set_tb(timebase >> 32, timebase & 0xffffffff); in pas_take_timebase()
129 timebase = 0; in pas_take_timebase()
152 reset_reg = ioremap(0xfc101100, 4); in pas_setup_arch()
162 reg = 0; in pas_setup_mce_regs()
[all …]
/linux/arch/arm/mach-sa1100/
H A Dgeneric.c70 return 0; in sa11x0_getspeed()
71 return sa11x0_freq_table[PPCR & 0xf].frequency; in sa11x0_getspeed()
89 PSPR = 0; in sa1100_power_off()
99 /* Jump into ROM at address 0 */ in sa11x0_restart()
100 soft_restart(0); in sa11x0_restart()
119 [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
123 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
130 .coherent_dma_mask = 0xffffffff,
137 [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
149 [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
[all …]
/linux/arch/arm/probes/kprobes/
H A Dtest-thumb.c26 kprobe_test_cc_position = 0;
34 " mov r1, #0x11 \n\t" \
35 " mov r2, #0x22 \n\t" \
36 " mov r3, #0x33 \n\t" \
65 TEST_R( "lsls r7, r",0,VAL1,", #5") in kprobe_thumb16_test_cases()
67 TEST_R( "lsrs r7, r",0,VAL1,", #5") in kprobe_thumb16_test_cases()
69 TEST_R( "asrs r7, r",0,VAL1,", #5") in kprobe_thumb16_test_cases()
71 TEST_RR( "adds r2, r",0,VAL1,", r",7,VAL2,"") in kprobe_thumb16_test_cases()
72 TEST_RR( "adds r5, r",7,VAL2,", r",0,VAL2,"") in kprobe_thumb16_test_cases()
73 TEST_RR( "subs r2, r",0,VAL1,", r",7,VAL2,"") in kprobe_thumb16_test_cases()
[all …]
H A Dtest-arm.c53 kprobe_test_flags = 0; in kprobe_arm_test_cases()
69 TEST_RRR( op s "hi r8, r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\ in kprobe_arm_test_cases()
74 TEST_RR( op s "le r14, r",0, val, ", r13" ", lsl r",14,8,"")\ in kprobe_arm_test_cases()
75 TEST_R( op s "eq r0, r",11,VAL1,", #0xf5") \ in kprobe_arm_test_cases()
76 TEST_R( op s "ne r11, r",0, VAL1,", #0xf5000000") \ in kprobe_arm_test_cases()
77 TEST_R( op s " r7, r",8, VAL2,", #0x000af000") \ in kprobe_arm_test_cases()
78 TEST( op s " r4, pc" ", #0x00005a00") in kprobe_arm_test_cases()
96 TEST_RRR( op "ls r",9, VAL1,", r",14,val, ", lsl r",0, 3,"") \ in kprobe_arm_test_cases()
101 TEST_RR( op "gt r",0, val, ", r13" ", lsl r",14,8,"") \ in kprobe_arm_test_cases()
102 TEST_R( op "eq r",11,VAL1,", #0xf5") \ in kprobe_arm_test_cases()
[all …]
/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660.dtsi25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
75 reg = <0x0 0x1>;
88 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
114 reg = <0x0 0x100>;
128 reg = <0x0 0x101>;
141 reg = <0x0 0x102>;
154 reg = <0x0 0x103>;
[all …]