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Searched +full:0 +full:xf145 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/media/dvb-frontends/
H A Dstb0899_drv.h40 #define STB0899_GPIO00 0xf140
41 #define STB0899_GPIO01 0xf141
42 #define STB0899_GPIO02 0xf142
43 #define STB0899_GPIO03 0xf143
44 #define STB0899_GPIO04 0xf144
45 #define STB0899_GPIO05 0xf145
46 #define STB0899_GPIO06 0xf146
47 #define STB0899_GPIO07 0xf147
48 #define STB0899_GPIO08 0xf148
49 #define STB0899_GPIO09 0xf149
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H A Dstb0899_reg.h14 #define STB0899_DEV_ID 0xf000
15 #define STB0899_CHIP_ID (0x0f << 4)
18 #define STB0899_CHIP_REL (0x0f << 0)
19 #define STB0899_OFFST_CHIP_REL 0
22 #define STB0899_DEMOD 0xf40e
23 #define STB0899_MODECOEFF (0x01 << 0)
24 #define STB0899_OFFST_MODECOEFF 0
27 #define STB0899_RCOMPC 0xf410
28 #define STB0899_AGC1CN 0xf412
29 #define STB0899_AGC1REF 0xf413
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H A Dstv0900_reg.h17 #define REGx(x) shiftx(x, demod, 0x200)
18 #define FLDx(x) shiftx(x, demod, 0x2000000)
21 #define R0900_MID 0xf100
22 #define F0900_MCHIP_IDENT 0xf10000f0
23 #define F0900_MRELEASE 0xf100000f
26 #define R0900_DACR1 0xf113
27 #define F0900_DAC_MODE 0xf11300e0
28 #define F0900_DAC_VALUE1 0xf113000f
31 #define R0900_DACR2 0xf114
32 #define F0900_DAC_VALUE0 0xf11400ff
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H A Dstv0910_regs.h18 #define RSTV0910_MID 0xf100
19 #define FSTV0910_MCHIP_IDENT 0xf10040f0
20 #define FSTV0910_MRELEASE 0xf100000f
23 #define RSTV0910_DID 0xf101
24 #define FSTV0910_DEVICE_ID 0xf10100ff
27 #define RSTV0910_DACR1 0xf113
28 #define FSTV0910_DAC_MODE 0xf11350e0
29 #define FSTV0910_DAC_VALUE1 0xf113000f
32 #define RSTV0910_DACR2 0xf114
33 #define FSTV0910_DAC_VALUE0 0xf11400ff
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/linux/drivers/mfd/
H A Dwm8994-regmap.c18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
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/linux/sound/soc/codecs/
H A Dmsm8916-wcd-analog.c19 #define CDC_D_REVISION1 (0xf000)
20 #define CDC_D_PERPH_SUBTYPE (0xf005)
21 #define CDC_D_INT_EN_SET (0xf015)
22 #define CDC_D_INT_EN_CLR (0xf016)
27 #define CDC_D_CDC_RST_CTL (0xf046)
29 #define RST_CTL_DIG_SW_RST_N_RESET 0
32 #define CDC_D_CDC_TOP_CLK_CTL (0xf048)
37 #define CDC_D_CDC_ANA_CLK_CTL (0xf049)
38 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
39 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
[all …]
H A Dwm8996.c110 return 0; \
113 WM8996_REGULATOR_EVENT(0)
118 { WM8996_POWER_MANAGEMENT_1, 0x0 },
119 { WM8996_POWER_MANAGEMENT_2, 0x0 },
120 { WM8996_POWER_MANAGEMENT_3, 0x0 },
121 { WM8996_POWER_MANAGEMENT_4, 0x0 },
122 { WM8996_POWER_MANAGEMENT_5, 0x0 },
123 { WM8996_POWER_MANAGEMENT_6, 0x0 },
124 { WM8996_POWER_MANAGEMENT_7, 0x10 },
125 { WM8996_POWER_MANAGEMENT_8, 0x
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H A Dwm8962.c101 return 0; \
104 WM8962_REGULATOR_EVENT(0)
114 { 0, 0x009F }, /* R0 - Left Input volume */
115 { 1, 0x049F }, /* R1 - Right Input volume */
116 { 2, 0x0000 }, /* R2 - HPOUTL volume */
117 { 3, 0x0000 }, /* R3 - HPOUTR volume */
119 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
120 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
121 { 7, 0x000A }, /* R7 - Audio Interface 0 */
122 { 8, 0x01E4 }, /* R8 - Clocking2 */
[all …]