Searched +full:0 +full:xf0800000 (Results 1 – 8 of 8) sorted by relevance
17 #define SH_CCR 0xfffc1000 /* CCR1 */18 #define SH_CCR2 0xfffc100424 #define CCR_CACHE_CB 0x0000 /* Hack */25 #define CCR_CACHE_OCE 0x000126 #define CCR_CACHE_WT 0x000227 #define CCR_CACHE_OCI 0x0008 /* OCF */28 #define CCR_CACHE_ICE 0x010029 #define CCR_CACHE_ICI 0x0800 /* ICF */31 #define CACHE_IC_ADDRESS_ARRAY 0xf000000032 #define CACHE_OC_ADDRESS_ARRAY 0xf0800000[all …]
37 reg = <0xf0800000 0x10000>;
7 #define UART_CR_OFFSET 0x00 /* Control Register [8:0] */8 #define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */9 #define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */11 #define UART_SR_TXFULL 0x00000010 /* TX FIFO full */12 #define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */14 #define UART0_PHYS 0xE000000015 #define UART0_VIRT 0xF080000016 #define UART1_PHYS 0xE000100017 #define UART1_VIRT 0xF0801000
17 * f0800000 PCIe #0 I/O space29 * fee00000 f0800000 64K PCIe #0 I/O space39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf102000040 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf102400041 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe40000045 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))48 #define MV78XX0_REGS_PHYS_BASE 0xf100000049 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)[all …]
22 #define ASP_VER_OFFSET 0x20 /* offset of ASP version */24 #define ASP_LED_ADDR 0xf080002026 #define VIPER_INT_WORD 0xFFFBF088 /* addr of viper interrupt word */35 case 0x71: irq = 9; break; /* SCSI */ in asp_choose_irq()36 case 0x72: irq = 8; break; /* LAN */ in asp_choose_irq()37 case 0x73: irq = 1; break; /* HIL */ in asp_choose_irq()38 case 0x74: irq = 7; break; /* Centronics */ in asp_choose_irq()39 case 0x75: irq = (dev->hw_path == 4) ? 5 : 6; break; /* RS232 */ in asp_choose_irq()40 case 0x76: irq = 10; break; /* EISA BA */ in asp_choose_irq()41 case 0x77: irq = 11; break; /* Graphics1 */ in asp_choose_irq()[all …]
42 reg = <0 0xb2000000 0 0x1800000>;47 reg = <0 0x8c415000 0 0x2000>;52 reg = <0 0x8c400000 0 0x10000>;57 reg = <0 0x8c500000 0 0x1e00000>;62 reg = <0 0x8e300000 0 0x100000>;67 reg = <0 0x8e400000 0 0x8900000>;72 reg = <0 0x96d00000 0 0x500000>;77 reg = <0 0x97200000 0 0x800000>;82 reg = <0 0x97a00000 0 0x200000>;87 reg = <0 0x97c00000 0 0x1400000>;[all …]
42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \44 '0' + (init->nested - 1) : ' ', ##args); \45 } while(0)49 } while(0)67 if (exec) init->execute &= 0xfd; in init_exec_set()68 else init->execute |= 0x02; in init_exec_set()74 init->execute ^= 0x02; in init_exec_inv()80 if (exec) init->execute |= 0x04; in init_exec_force()81 else init->execute &= 0xfb; in init_exec_force()92 if (init->or >= 0) in init_or()[all …]
23 #size-cells = <0>;25 cpu0: cpu@0 {28 reg = <0x0>;30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;31 i-cache-size = <0xc000>;34 d-cache-size = <0x8000>;45 reg = <0x1>;47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;48 i-cache-size = <0xc000>;51 d-cache-size = <0x8000>;[all …]