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/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Ddma.h19 #define B43_DMA32_TXCTL 0x00
20 #define B43_DMA32_TXENABLE 0x00000001
21 #define B43_DMA32_TXSUSPEND 0x00000002
22 #define B43_DMA32_TXLOOPBACK 0x00000004
23 #define B43_DMA32_TXFLUSH 0x00000010
24 #define B43_DMA32_TXPARITYDISABLE 0x00000800
25 #define B43_DMA32_TXADDREXT_MASK 0x00030000
27 #define B43_DMA32_TXRING 0x04
28 #define B43_DMA32_TXINDEX 0x08
29 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/linux/arch/arc/boot/dts/
H A Dnsim_700.dts17 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signal…
33 #clock-cells = <0>;
46 reg = <0xf0000000 0x2000>;
H A Dhaps_hs_idu.dts18 reg = <0x80000000 0x20000000>; /* 512 */
22 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
38 #clock-cells = <0>;
58 reg = <0xf0000000 0x2000>;
60 interrupts = <0>;
H A Dnsimosci.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
H A Dnsimosci_hs.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
H A Dhaps_hs.dts19 reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */
20 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
24 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
38 ranges = <0x80000000 0x0 0x80000000 0x80000000>;
41 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
71 reg = <0xf0100000 0x2000>;
77 reg = <0xf0102000 0x2000>;
83 reg = <0xf0104000 0x2000>;
89 reg = <0xf0106000 0x2000>;
[all …]
H A Dnsimosci_hs_idu.dts18 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
34 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
56 interrupts = <0>;
65 #clock-cells = <0>;
72 reg = <0xf9000000 0x400>;
79 reg = <0xf9000400 0x14>;
87 reg = <0xf0003000 0x44>;
/linux/arch/xtensa/include/asm/
H A Dkmem_layout.h23 #define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000)
24 #define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000)
28 #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
29 #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
30 #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
31 #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000)
37 #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000)
38 #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
39 #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000)
40 #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
[all …]
/linux/arch/sparc/lib/
H A Dfls.S16 mov 0, %o1
17 sethi %hi(0xffff0000), %g3
22 sethi %hi(0xff000000), %g3
25 sethi %hi(0xf0000000), %g3
29 sra %o0, 0, %o0
32 sethi %hi(0xf0000000), %g3
36 sethi %hi(0xc0000000), %g3
39 sra %o0, 0, %o0
51 sra %o1, 0, %o0
55 sra %o0, 0, %o0
[all …]
/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dintegratorap.dts17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-gp.dts13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
17 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
41 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
45 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
46 <0x00000001 0x00000000 0x00000001 0x00000000>;
58 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
59 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
60 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt24 0 <physical address of mapping> <size>
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
53 ALE[0] to the cycle that the first read data is sampled
63 DEV_OEn assertion. If set to 0 (default),
72 de-assertion of DEV_CSn. If set to 0 (default),
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
90 A[2:0] and Data are kept valid as long as DEV_WEn
97 DEV_A[2:0] and Data are kept valid (do not toggle) for
105 0: False
115 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
[all …]
/linux/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/Documentation/arch/xtensa/
H A Dmmu.rst16 - RASID is 0x04030201 (reset state).
28 After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
29 or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
30 0x40000000 or above. That address corresponds to next instruction to execute
32 The scheme below assumes that the kernel is loaded below 0x40000000.
49 The default location of IO peripherals is above 0xf0000000. This may be changed
75 | Userspace | 0x00000000 TASK_SIZE
76 +------------------+ 0x40000000
78 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
80 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
[all …]
/linux/arch/powerpc/boot/dts/
H A Da3m071.dts26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
41 reg = <0x2000 0x100>;
42 interrupts = <2 1 0>;
63 reg = <0x2c00 0x100>;
64 interrupts = <2 4 0>;
73 reg = <0x03>;
94 ranges = <0 0 0xfc000000 0x02000000
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpdma0_qm_masks.h24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
H A Ddcore0_edma0_qm_masks.h24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8135-apmixedsys.c38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2…
41 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23…
42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
47 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
[all …]

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