Searched +full:0 +full:xe89 (Results 1 – 10 of 10) sorted by relevance
15 - #clock-cells: Shall be 032 reg = <0xe89>;37 interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */38 #clock-cells = <0>;45 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
24 const: 091 #size-cells = <0>;95 reg = <0xe89>;100 interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */101 #clock-cells = <0>;108 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
5 # fault virtual address = 0x5eb9977d7 # instruction pointer = 0x20:0xffffffff80d8f1818 # stack pointer = 0x28:0xfffffe01267093009 # frame pointer = 0x28:0xfffffe012670975010 # code segment = base 0x0, limit 0xfffff, type 0x1b11 # = DPL 0, pres 1, long 1, def32 0, gran 112 # processor eflags = interrupt enabled, resume, IOPL = 013 # current process = 12 (swi1: netisr 0)19 # db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe0126708fb020 # vpanic() at vpanic+0x182/frame 0xfffffe0126709000[all …]
50 model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";68 gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */78 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */96 pinctrl-0 = <&mmc0_pins>;105 pinctrl-0 = <&mmc2_8bit_emmc_pins>;123 reg = <0x3a3>;132 reg = <0xe89>;137 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */138 #clock-cells = <0>;268 pinctrl-0 = <&uart0_pb_pins>;
77 led-0 {84 gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */146 pinctrl-0 = <&emac_rgmii_pins>;174 pinctrl-0 = <&mmc0_pins>;193 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;200 pinctrl-0 = <&mmc2_8bit_emmc_pins>;219 reg = <0x3a3>;230 reg = <0xe89>;235 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */[all …]
66 led-0 {95 #size-cells = <0>;97 port@0 {98 reg = <0>;120 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */130 pinctrl-0 = <&gmac_rgmii_pins>;139 pinctrl-0 = <&i2c3_pins>;151 pinctrl-0 = <&mmc0_pins>;160 pinctrl-0 = <&mmc1_pins>;175 pinctrl-0 = <&mmc2_8bit_pins>;[all …]
77 led-0 {126 gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */143 #sound-dai-cells = <0>;155 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */183 pinctrl-0 = <&emac_rgmii_pins>;209 pinctrl-0 = <&mmc0_pins>;227 pinctrl-0 = <&mmc2_8bit_emmc_pins>;240 reg = <0x3a3>;250 reg = <0xe89>;255 interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */[all …]
66 pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;69 brightness-levels = <0 1 2 4 8 16 32 64 128 255>;121 gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;128 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */173 reg = <0x38>;175 interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */189 reg = <0x18>;198 pinctrl-0 = <&mmc0_pins>;218 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */224 pinctrl-0 = <&mmc2_8bit_emmc_pins>;[all …]
79 gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>;106 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */125 pinctrl-0 = <&gmac_rgmii_pins>;140 pinctrl-0 = <&mmc0_pins>;149 pinctrl-0 = <&mmc1_pins>;164 pinctrl-0 = <&mmc2_8bit_pins>;187 clocks = <&ac100_rtc 0>;214 reg = <0x3a3>;216 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;345 reg = <0x745>;[all …]
51 #define RSB_CTRL 0x0054 #define SOFT_RESET (1 << 0)55 #define RSB_CCR 0x0456 #define RSB_INTE 0x0857 #define RSB_INTS 0x0c58 #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf)61 #define INT_TRANS_OVER (1 << 0)63 #define RSB_DADDR0 0x1064 #define RSB_DADDR1 0x1465 #define RSB_DLEN 0x18[all …]