Searched +full:0 +full:xe6a00000 (Results 1 – 7 of 7) sorted by relevance
52 - #size-cells: number of size cells on the MDIO bus, must be equal to 0.54 - pinctrl-0: phandle, referring to a default pin configuration node.60 where %u is the channel number ranging from 0 to 24.73 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;112 pinctrl-0 = <ðer_pins>;116 #size-cells = <0>;118 phy0: ethernet-phy@0 {120 rxdv-skew-ps = <0>;121 rxd0-skew-ps = <0>;122 rxd1-skew-ps = <0>;[all …]
107 const: 0126 enum: [0, 1800]129 enum: [0, 2000]135 "@[0-9a-f]$":203 pattern: '^(ch(1?)[0-9])|ch20|ch21|dia|dib|err_a|err_b|mgmt_a|mgmt_b|line3$'214 pattern: '^ch[0-9]+$'324 reg = <0xe6800000 0x800>, <0xe6a00000 0x10000>;361 rx-internal-delay-ps = <0>;364 #size-cells = <0>;366 phy0: ethernet-phy@0 {[all …]
18 * The external audio clocks are configured as 0 Hz fixed frequency24 #clock-cells = <0>;25 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;36 #clock-cells = <0>;37 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;47 cluster0_opp: opp-table-0 {[all …]
23 * The external audio clocks are configured as 0 Hz fixed frequency29 #clock-cells = <0>;30 clock-frequency = <0>;35 #clock-cells = <0>;36 clock-frequency = <0>;41 #clock-cells = <0>;42 clock-frequency = <0>;48 #clock-cells = <0>;49 clock-frequency = <0>;52 cluster0_opp: opp-table-0 {[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]