Searched +full:0 +full:xe6180000 (Results 1 – 17 of 17) sorted by relevance
19 #define CPG_BASE2 0xe615100020 #define WUPCR 0x10 /* System-CPU Wake Up Control Register */21 #define SRESCR 0x18 /* System-CPU Software Reset Control Register */22 #define PSTR 0x40 /* System-CPU Power Status Register */24 #define SYSC_BASE 0xe618000025 #define SBAR 0x20 /* SYS Boot Address Register */27 #define AP_BASE 0xe6f1000028 #define APARMBAREA 0x20 /* Address Translation Area Register */30 #define SH73A0_SCU_BASE 0xf000000042 return 0; in sh73a0_boot_secondary()[all …]
28 - renesas,r8a774a3-sysc # RZ/G2M v3.069 reg = <0xe6180000 0x0200>;
45 const: 077 const: 080 const: 095 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;100 #size-cells = <0>;101 #power-domain-cells = <0>;106 #size-cells = <0>;107 #power-domain-cells = <0>;111 #power-domain-cells = <0>;117 #power-domain-cells = <0>;
20 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;35 reg = <0xc2800000 0x1000>,36 <0xc2000000 0x1000>;41 reg = <0xf0100000 0x1000>;53 reg = <0xfe400000 0x400>;68 reg = <0xfe910000 0x3000>;77 reg = <0xfe914000 0x3000>;87 reg = <0xe6138000 0x170>;[all …]
27 #size-cells = <0>;29 cpu0: cpu@0 {32 reg = <0>;51 L2_CA7: cache-controller-0 {62 #clock-cells = <0>;64 clock-frequency = <0>;77 #clock-cells = <0>;79 clock-frequency = <0>;93 reg = <0 0xe6020000 0 0x0c>;104 reg = <0 0xe6050000 0 0x50>;[all …]
22 #clock-cells = <0>;23 clock-frequency = <0>;28 #size-cells = <0>;30 a53_0: cpu@0 {33 reg = <0>;60 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;69 clock-frequency = <0>;87 #clock-cells = <0>;[all …]
22 #clock-cells = <0>;23 clock-frequency = <0>;28 #size-cells = <0>;30 a53_0: cpu@0 {33 reg = <0>;80 #clock-cells = <0>;82 clock-frequency = <0>;87 #clock-cells = <0>;89 clock-frequency = <0>;95 #clock-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;31 #clock-cells = <0>;32 clock-frequency = <0>;38 #clock-cells = <0>;39 clock-frequency = <0>;44 #size-cells = <0>;46 a53_0: cpu@0 {48 reg = <0x0>;[all …]
18 * The external audio clocks are configured as 0 Hz fixed frequency24 #clock-cells = <0>;25 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;36 #clock-cells = <0>;37 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;67 #size-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;31 #clock-cells = <0>;32 clock-frequency = <0>;37 #clock-cells = <0>;38 clock-frequency = <0>;44 #clock-cells = <0>;45 clock-frequency = <0>;48 cluster0_opp: opp-table-0 {[all …]
18 * The external audio clocks are configured as 0 Hz fixed frequency24 #clock-cells = <0>;25 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;36 #clock-cells = <0>;37 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;47 cluster0_opp: opp-table-0 {[all …]
23 * The external audio clocks are configured as 0 Hz fixed frequency29 #clock-cells = <0>;30 clock-frequency = <0>;35 #clock-cells = <0>;36 clock-frequency = <0>;41 #clock-cells = <0>;42 clock-frequency = <0>;48 #clock-cells = <0>;49 clock-frequency = <0>;52 cluster0_opp: opp-table-0 {[all …]