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Searched +full:0 +full:xe4 (Results 1 – 25 of 541) sorted by relevance

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/linux/drivers/clk/hisilicon/
H A Dclk-hi3519.c35 { HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
36 { HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
37 { HI3519_FIXED_75M, "75m", NULL, 0, 75000000, },
38 { HI3519_FIXED_125M, "125m", NULL, 0, 125000000, },
39 { HI3519_FIXED_150M, "150m", NULL, 0, 150000000, },
40 { HI3519_FIXED_200M, "200m", NULL, 0, 200000000, },
41 { HI3519_FIXED_250M, "250m", NULL, 0, 250000000, },
42 { HI3519_FIXED_300M, "300m", NULL, 0, 300000000, },
43 { HI3519_FIXED_400M, "400m", NULL, 0, 400000000, },
48 static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
[all …]
H A Dcrg-hi3516cv300.c40 { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
41 { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
42 { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
43 { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
44 { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
45 { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
46 { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
47 { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
48 { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
49 { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-eth.c18 .set_ofs = 0xe4,
19 .clr_ofs = 0xe4,
20 .sta_ofs = 0xe4,
34 .set_ofs = 0xe4,
35 .clr_ofs = 0xe4,
36 .sta_ofs = 0xe4,
50 .set_ofs = 0x30,
51 .clr_ofs = 0x30,
52 .sta_ofs = 0x30,
H A Dclk-mt7622-eth.c21 .set_ofs = 0x30,
22 .clr_ofs = 0x30,
23 .sta_ofs = 0x30,
35 .set_ofs = 0xE4,
36 .clr_ofs = 0xE4,
37 .sta_ofs = 0xE4,
54 static u16 rst_ofs[] = { 0x34, };
H A Dclk-mt7988-eth.c20 .set_ofs = 0x30,
21 .clr_ofs = 0x30,
22 .sta_ofs = 0x30,
36 GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
53 .set_ofs = 0xe4,
54 .clr_ofs = 0xe4,
55 .sta_ofs = 0xe4,
89 .set_ofs = 0x14,
90 .clr_ofs = 0x14,
91 .sta_ofs = 0x14,
[all …]
H A Dclk-mt7629-eth.c21 .set_ofs = 0x30,
22 .clr_ofs = 0x30,
23 .sta_ofs = 0x30,
35 .set_ofs = 0xE4,
36 .clr_ofs = 0xE4,
37 .sta_ofs = 0xE4,
65 static u16 rst_ofs[] = { 0x34, };
/linux/drivers/char/
H A Dtoshiba.c11 * 0xfc02: Scott Eisert <scott.e@sky-eye.com>
12 * 0xfc04: Steve VanDevender <stevev@efn.org>
13 * 0xfc08: Garth Berry <garth@itsbruce.net>
14 * 0xfc0a: Egbert Eich <eich@xfree86.org>
15 * 0xfc10: Andrew Lofthouse <Andrew.Lofthouse@robins.af.mil>
16 * 0xfc11: Spencer Olson <solson@novell.com>
17 * 0xfc13: Claudius Frankewitz <kryp@gmx.de>
18 * 0xfc15: Tom May <tom@you-bastards.com>
19 * 0xfc17: Dave Konrad <konrad@xenia.it>
20 * 0xfc1a: George Betzos <betzos@engr.colostate.edu>
[all …]
/linux/drivers/media/dvb-frontends/
H A Ds5h1432.c40 } while (0)
48 struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 }; in s5h1432_writereg()
53 printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n", in s5h1432_writereg()
56 return (ret != 1) ? -1 : 0; in s5h1432_writereg()
63 u8 b1[] = { 0 }; in s5h1432_readreg()
66 {.addr = addr, .flags = 0, .buf = b0, .len = 1}, in s5h1432_readreg()
75 return b1[0]; in s5h1432_readreg()
80 return 0; in s5h1432_sleep()
88 u8 reg = 0; in s5h1432_set_channel_bandwidth()
90 /* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */ in s5h1432_set_channel_bandwidth()
[all …]
/linux/fs/nls/
H A Dnls_euc-jp.c17 #define IS_SJIS_LOW_BYTE(l) ((0x40 <= (l)) && ((l) <= 0xFC) && ((l) != 0x7F))
19 #define IS_SJIS_JISX0208(h, l) ((((0x81 <= (h)) && ((h) <= 0x9F)) \
20 || ((0xE0 <= (h)) && ((h) <= 0xEA))) \
22 #define IS_SJIS_JISX0201KANA(c) ((0xA1 <= (c)) && ((c) <= 0xDF))
23 #define IS_SJIS_UDC_LOW(h, l) (((0xF0 <= (h)) && ((h) <= 0xF4)) \
25 #define IS_SJIS_UDC_HI(h, l) (((0xF5 <= (h)) && ((h) <= 0xF9)) \
27 #define IS_SJIS_IBM(h, l) (((0xFA <= (h)) && ((h) <= 0xFC)) \
29 #define IS_SJIS_NECIBM(h, l) (((0xED <= (h)) && ((h) <= 0xEE)) \
32 if ((sjis_lo) >= 0x9F) { \
37 (euc_lo) = (sjis_lo) + ((sjis_lo) >= 0x7F ? 0x60 : 0x61); \
[all …]
H A Dnls_cp932.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x3000,0x3001,0x3002,0xFF0C,0xFF0E,0x30FB,0xFF1A,0xFF1B,/* 0x40-0x47 */
26 0xFF1F,0xFF01,0x309B,0x309C,0x00B4,0xFF40,0x00A8,0xFF3E,/* 0x48-0x4F */
[all …]
H A Dnls_cp950.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x3000,0xFF0C,0x3001,0x3002,0xFF0E,0x2027,0xFF1B,0xFF1A,/* 0x40-0x47 */
26 0xFF1F,0xFF01,0xFE30,0x2026,0x2025,0xFE50,0xFE51,0xFE52,/* 0x48-0x4F */
[all …]
H A Dnls_cp936.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x4E02,0x4E04,0x4E05,0x4E06,0x4E0F,0x4E12,0x4E17,0x4E1F,/* 0x40-0x47 */
26 0x4E20,0x4E21,0x4E23,0x4E26,0x4E29,0x4E2E,0x4E2F,0x4E31,/* 0x48-0x4F */
[all …]
/linux/drivers/target/
H A Dtarget_core_xcopy.c42 * @return: 1 on match, 0 on no-match
52 return 0; in target_xcopy_locate_se_dev_e4_iter()
55 memset(&tmp_dev_wwn[0], 0, XCOPY_NAA_IEEE_REGEX_LEN); in target_xcopy_locate_se_dev_e4_iter()
56 spc_gen_naa_6h_vendor_specific(se_dev, &tmp_dev_wwn[0]); in target_xcopy_locate_se_dev_e4_iter()
58 rc = memcmp(&tmp_dev_wwn[0], dev_wwn, XCOPY_NAA_IEEE_REGEX_LEN); in target_xcopy_locate_se_dev_e4_iter()
59 if (rc != 0) { in target_xcopy_locate_se_dev_e4_iter()
62 return 0; in target_xcopy_locate_se_dev_e4_iter()
64 pr_debug("XCOPY 0xe4: located se_dev: %p\n", se_dev); in target_xcopy_locate_se_dev_e4_iter()
83 pr_debug("XCOPY 0xe4: searching for: %*ph\n", in target_xcopy_locate_se_dev_e4()
110 return 0; in target_xcopy_locate_se_dev_e4()
[all …]
/linux/drivers/platform/x86/
H A Dmsi-ec.c50 .address = 0xef,
51 .offset_start = 0x8a,
52 .offset_end = 0x80,
53 .range_min = 0x8a,
54 .range_max = 0xe4,
57 .address = 0x2e,
58 .block_address = 0x2f,
62 .address = 0xbf,
66 .address = 0x98,
70 .address = 0xf2,
[all …]
/linux/lib/crypto/tests/
H A Dsha512-testvecs.h9 .data_len = 0,
11 0xcf, 0x83, 0xe1, 0x35, 0x7e, 0xef, 0xb8, 0xbd,
12 0xf1, 0x54, 0x28, 0x50, 0xd6, 0x6d, 0x80, 0x07,
13 0xd6, 0x20, 0xe4, 0x05, 0x0b, 0x57, 0x15, 0xdc,
14 0x83, 0xf4, 0xa9, 0x21, 0xd3, 0x6c, 0xe9, 0xce,
15 0x47, 0xd0, 0xd1, 0x3c, 0x5d, 0x85, 0xf2, 0xb0,
16 0xff, 0x83, 0x18, 0xd2, 0x87, 0x7e, 0xec, 0x2f,
17 0x63, 0xb9, 0x31, 0xbd, 0x47, 0x41, 0x7a, 0x81,
18 0xa5, 0x38, 0x32, 0x7a, 0xf9, 0x27, 0xda, 0x3e,
24 0x12, 0xf2, 0xb6, 0xec, 0x84, 0xa0, 0x8e, 0xcf,
[all …]
H A Dsha3-testvecs.h11 .data_len = 0,
13 0xa7, 0xff, 0xc6, 0xf8, 0xbf, 0x1e, 0xd7, 0x66,
14 0x51, 0xc1, 0x47, 0x56, 0xa0, 0x61, 0xd6, 0x62,
15 0xf5, 0x80, 0xff, 0x4d, 0xe4, 0x3b, 0x49, 0xfa,
16 0x82, 0xd8, 0x0a, 0x4b, 0x80, 0xf8, 0x43, 0x4a,
22 0x11, 0x03, 0xe7, 0x84, 0x51, 0x50, 0x86, 0x35,
23 0x71, 0x8a, 0x70, 0xe3, 0xc4, 0x26, 0x7b, 0x21,
24 0x02, 0x13, 0xa0, 0x81, 0xe8, 0xe6, 0x14, 0x25,
25 0x07, 0x34, 0xe5, 0xc5, 0x40, 0x06, 0xf2, 0x8b,
31 0x2f, 0x6f, 0x6d, 0x47, 0x48, 0x52, 0x11, 0xb9,
[all …]
H A Dsha256-testvecs.h9 .data_len = 0,
11 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14,
12 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24,
13 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c,
14 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55,
20 0x45, 0xf8, 0x3d, 0x17, 0xe1, 0x0b, 0x34, 0xfc,
21 0xa0, 0x1e, 0xb8, 0xf4, 0x45, 0x4d, 0xac, 0x34,
22 0xa7, 0x77, 0xd9, 0x40, 0x4a, 0x46, 0x4e, 0x73,
23 0x2c, 0xf4, 0xab, 0xf2, 0xc0, 0xda, 0x94, 0xc4,
29 0xf9, 0xd3, 0x52, 0x2f, 0xd5, 0xe0, 0x99, 0x15,
[all …]
H A Dsha1-testvecs.h9 .data_len = 0,
11 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d,
12 0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90,
13 0xaf, 0xd8, 0x07, 0x09,
19 0x0a, 0xd0, 0x52, 0xdd, 0x9f, 0x32, 0x40, 0x55,
20 0x21, 0xe4, 0x3c, 0x6e, 0xbd, 0xc5, 0x2f, 0x5a,
21 0x02, 0x54, 0x93, 0xb2,
27 0x13, 0x83, 0x82, 0x03, 0x23, 0xff, 0x46, 0xd6,
28 0x12, 0x7f, 0xad, 0x05, 0x2b, 0xc3, 0x4a, 0x42,
29 0x49, 0x6a, 0xf8, 0x84,
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-regs.h11 * locates in one single space starts from 0 but in different sctions with
12 * different addresses, the subsystem offsets are defined to 0 as the
13 * register definition will have the address offset to 0.
15 #define IPU6_UNIFIED_OFFSET 0
17 #define IPU6_ISYS_IOMMU0_OFFSET 0x2e0000
18 #define IPU6_ISYS_IOMMU1_OFFSET 0x2e0500
19 #define IPU6_ISYS_IOMMUI_OFFSET 0x2e0a00
21 #define IPU6_PSYS_IOMMU0_OFFSET 0x1b0000
22 #define IPU6_PSYS_IOMMU1_OFFSET 0x1b0700
23 #define IPU6_PSYS_IOMMU1R_OFFSET 0x1b0e00
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Dp54spi_eeprom.h19 0x47, 0x4d, 0x55, 0xaa, /* magic */
20 0x00, 0x00, /* pad */
21 0x00, 0x00, /* eeprom_pda_data_wrap length */
22 0x00, 0x00, 0x00, 0x00, /* arm opcode */
25 0x04, 0x00, 0x01, 0x01, /* PDR_MAC_ADDRESS */
26 0x00, 0x02, 0xee, 0xc0, 0xff, 0xee,
29 0x06, 0x00, 0x01, 0x10, /* PDR_INTERFACE_LIST */
30 0x00, 0x00, /* role */
31 0x0f, 0x00, /* if_id */
32 0x85, 0x00, /* variant = Longbow RF, 2GHz */
[all …]
/linux/drivers/scsi/
H A Dscsi_proto_test.c14 } d = { .arr = { 0x45, 0, 0, 0, 0xb0, 0xe4, 0xe3 } }; in test_scsi_proto()
15 KUNIT_EXPECT_EQ(test, d.desc.io_advice_hints_mode + 0, 1); in test_scsi_proto()
16 KUNIT_EXPECT_EQ(test, d.desc.st_enble + 0, 1); in test_scsi_proto()
17 KUNIT_EXPECT_EQ(test, d.desc.cs_enble + 0, 0); in test_scsi_proto()
18 KUNIT_EXPECT_EQ(test, d.desc.ic_enable + 0, 1); in test_scsi_proto()
19 KUNIT_EXPECT_EQ(test, d.desc.acdlu + 0, 1); in test_scsi_proto()
20 KUNIT_EXPECT_EQ(test, d.desc.rlbsr + 0, 3); in test_scsi_proto()
21 KUNIT_EXPECT_EQ(test, d.desc.lbm_descriptor_type + 0, 0); in test_scsi_proto()
22 KUNIT_EXPECT_EQ(test, d.desc.params[0] + 0, 0xe4); in test_scsi_proto()
23 KUNIT_EXPECT_EQ(test, d.desc.params[1] + 0, 0xe3); in test_scsi_proto()
[all …]
/linux/drivers/media/usb/gspca/
H A Dtopro.c22 0xff, 0xd8, /* jpeg */
25 0xff, 0xdb, 0x00, 0x84, /* DQT */
26 0,
28 0x10, 0x0b, 0x0c, 0x0e, 0x0c, 0x0a, 0x10, 0x0e,
29 0x0d, 0x0e, 0x12, 0x11, 0x10, 0x13, 0x18, 0x28,
30 0x1a, 0x18, 0x16, 0x16, 0x18, 0x31, 0x23, 0x25,
31 0x1d, 0x28, 0x3a, 0x33, 0x3d, 0x3c, 0x39, 0x33,
32 0x38, 0x37, 0x40, 0x48, 0x5c, 0x4e, 0x40, 0x44,
33 0x57, 0x45, 0x37, 0x38, 0x50, 0x6d, 0x51, 0x57,
34 0x5f, 0x62, 0x67, 0x68, 0x67, 0x3e, 0x4d, 0x71,
[all …]
/linux/Documentation/devicetree/bindings/power/reset/
H A Dkeystone-reset.txt32 in format: <0>, <2>; It can be in random order and
33 begins from 0 to 3, as keystone can contain up to 4 SoC
42 reg = <0x02310000 0x200>;
47 reg = <0x02620000 0x1000>;
52 ti,syscon-pll = <&pllctrl 0xe4>;
53 ti,syscon-dev = <&devctrl 0x328>;
54 ti,wdt-list = <0>;
63 ti,syscon-pll = <&pllctrl 0xe4>;
64 ti,syscon-dev = <&devctrl 0x328>;
65 ti,wdt-list = <0>, <2>;
/linux/drivers/ufs/host/
H A Dufs-hisi.h14 #define PSW_POWER_CTRL (0x04)
15 #define PHY_ISO_EN (0x08)
16 #define HC_LP_CTRL (0x0C)
17 #define PHY_CLK_CTRL (0x10)
18 #define PSW_CLK_CTRL (0x14)
19 #define CLOCK_GATE_BYPASS (0x18)
20 #define RESET_CTRL_EN (0x1C)
21 #define UFS_SYSCTRL (0x5C)
22 #define UFS_DEVICE_RESET_CTRL (0x60)
25 #define BIT_UFS_PSW_MTCMOS_EN (1 << 0)
[all …]
/linux/arch/x86/kernel/cpu/microcode/
H A Damd_shas.c3 { 0x8001227, {
4 0x99,0xc0,0x9b,0x2b,0xcc,0x9f,0x52,0x1b,
5 0x1a,0x5f,0x1d,0x83,0xa1,0x6c,0xc4,0x46,
6 0xe2,0x6c,0xda,0x73,0xfb,0x2d,0x23,0xa8,
7 0x77,0xdc,0x15,0x31,0x33,0x4a,0x46,0x18,
10 { 0x8001250, {
11 0xc0,0x0b,0x6b,0x19,0xfd,0x5c,0x39,0x60,
12 0xd5,0xc3,0x57,0x46,0x54,0xe4,0xd1,0xaa,
13 0xa8,0xf7,0x1f,0xa8,0x6a,0x60,0x3e,0xe3,
14 0x27,0x39,0x8e,0x53,0x30,0xf8,0x49,0x19,
[all …]

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