Searched +full:0 +full:xe3120 (Results 1 – 7 of 7) sorted by relevance
2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ]37 cell-index = <0x9>;39 reg = <0x89000 0x1000>;43 cell-index = <0x29>;45 reg = <0xa9000 0x1000>;51 reg = <0xe2000 0x1000>;59 #size-cells = <0>;61 reg = <0xe3120 0xee0>;64 reg = <0x8>;
2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ]37 cell-index = <0x9>;39 reg = <0x89000 0x1000>;43 cell-index = <0x29>;45 reg = <0xa9000 0x1000>;51 reg = <0xe2000 0x1000>;59 #size-cells = <0>;61 reg = <0xe3120 0xee0>;64 reg = <0x8>;
93 reg = <0xf1000 0x1000>;94 interrupts = <101 2 0 0>;100 reg = <0xe3120 0xee0>;103 #size-cells = <0>;106 reg = <0x8>;114 reg = <0xf1000 0x1000>;117 #size-cells = <0>;119 pcsphy6: ethernet-phy@0 {120 reg = <0x0>;
28 FMan block. The offset is 0xc4 from the beginning of the29 Frame Processing Manager memory map (0xc3000 from the44 DEVDISR[1] 1 049 DCFG_DEVDISR2[6] 1 056 DCFG_CCSR_DEVDISR2[24] 1 0148 muram@0 {150 ranges = <0 0x000000 0x28000>;215 cell-index = <0x28>;217 reg = <0xa8000 0x1000>;221 cell-index = <0x8>;[all …]
103 #size-cells = <0>;105 cpu0: PowerPC,e500mc@0 {107 reg = <0>;145 dcsr-epu@0 {147 interrupts = <52 2 0 0148 84 2 0 0149 85 2 0 0>;151 reg = <0x0 0x1000>;155 reg = <0x1000 0x1000 0x1000000 0x8000>;159 reg = <0x2000 0x1000>;[all …]
102 #size-cells = <0>;104 cpu0: PowerPC,e500mc@0 {106 reg = <0>;144 dcsr-epu@0 {146 interrupts = <52 2 0 0147 84 2 0 0148 85 2 0 0>;150 reg = <0x0 0x1000>;154 reg = <0x1000 0x1000 0x1000000 0x8000>;158 reg = <0x2000 0x1000>;[all …]
109 #size-cells = <0>;111 cpu0: PowerPC,e5500@0 {113 reg = <0>;135 dcsr-epu@0 {137 interrupts = <52 2 0 0138 84 2 0 0139 85 2 0 0>;141 reg = <0x0 0x1000>;145 reg = <0x1000 0x1000 0x1000000 0x8000>;149 reg = <0x2000 0x1000>;[all …]