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Searched +full:0 +full:xe2000000 (Results 1 – 25 of 25) sorted by relevance

/linux/arch/mips/jazz/
H A Dirq.c62 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); in init_r4030_ints()
69 * driver compatibility reasons interrupts 0 - 15 to be the i8259
79 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ in arch_init_irq()
80 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); in arch_init_irq()
81 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ in arch_init_irq()
82 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M); in arch_init_irq()
83 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ in arch_init_irq()
84 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M); in arch_init_irq()
106 if (likely(irq > 0)) in plat_irq_dispatch()
H A Dsetup.c30 .start = 0x00,
31 .end = 0x1f,
35 .start = 0x40,
36 .end = 0x5f,
40 .start = 0x80,
41 .end = 0x8f,
45 .start = 0xc0,
46 .end = 0xdf,
56 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ in plat_mem_setup()
57 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); in plat_mem_setup()
[all …]
/linux/arch/arm/mach-bcm/
H A Dboard_bcm281xx.c11 #define SECWDOG_OFFSET 0x00000000
12 #define SECWDOG_RESERVED_MASK 0xe2000000
13 #define SECWDOG_WD_LOAD_FLAG_MASK 0x10000000
14 #define SECWDOG_EN_MASK 0x08000000
15 #define SECWDOG_SRSTEN_MASK 0x04000000
17 #define SECWDOG_COUNT_SHIFT 0
30 base = of_iomap(np_wdog, 0); in bcm281xx_restart()
41 (0x15 << SECWDOG_CLKS_SHIFT) | in bcm281xx_restart()
42 (0x8 << SECWDOG_COUNT_SHIFT); in bcm281xx_restart()
/linux/Documentation/devicetree/bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml37 reg = <0xe000e000 0x0001000>;
40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
46 nfc0: nand-controller@0,0 {
48 reg = <0 0 0x1000000>;
50 #size-cells = <0>;
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl35x-smc.yaml33 pattern: "^memory-controller@[0-9a-f]+$"
69 - description: Combined or Memory interface 0 IRQ
73 "@[0-7],[a-f0-9]+$":
91 minimum: 0
141 reg = <0xe000e000 0x0001000>;
144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
150 nfc0: nand-controller@0,0 {
152 reg = <0 0 0x1000000>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,lan966x-switch.yaml20 pattern: "^switch@[0-9a-f]+$"
68 const: 0
73 "^port@[0-9a-f]+$":
83 const: 0
143 reg = <0xe0000000 0x0100000>,
144 <0xe2000000 0x0800000>;
148 resets = <&switch_reset 0>;
152 #size-cells = <0>;
154 port0: port@0 {
155 reg = <0>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dspear600.dtsi12 #address-cells = <0>;
13 #size-cells = <0>;
23 reg = <0 0x40000000>;
30 ranges = <0xd0000000 0xd0000000 0x30000000>;
35 reg = <0xf1100000 0x1000>;
42 reg = <0xf1000000 0x1000>;
48 reg = <0xfc200000 0x1000>;
56 reg = <0xfc400000 0x1000>;
64 reg = <0xe0800000 0x8000>;
76 reg = <0xd1800000 0x1000 /* FSMC Register */
[all …]
H A Dspear13xx.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
36 reg = < 0xec801000 0x1000 >,
37 < 0xec800100 0x0100 >;
42 interrupts = <0 6 0x04>,
43 <0 7 0x04>;
48 reg = <0xed000000 0x1000>;
56 reg = <0 0x40000000>;
79 ranges = <0x50000000 0x50000000 0x10000000
[all …]
/linux/arch/mips/include/asm/
H A Djazz.h15 * but many hardware register are accessible at 0xb9000000 in
16 * instead of 0xe0000000.
19 #define JAZZ_LOCAL_IO_SPACE 0xe0000000
24 * 0xf0000000 - Rev1
25 * 0xf0000001 - Rev2
26 * 0xf0000002 - Rev3
28 #define PICA_ASIC_REVISION 0xe0000008
43 * --------- . (0)
45 #define PICA_LED 0xe000f000
54 #define LED_DOT 0x01
[all …]
/linux/arch/powerpc/boot/dts/
H A Dstx_gp3_8560.dts27 #size-cells = <0>;
29 PowerPC,8560@0 {
31 reg = <0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x10000000>;
52 ranges = <0 0xfdf00000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
[all …]
H A Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
H A Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
H A Dtqm8541.dts28 #size-cells = <0>;
30 PowerPC,8541@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8555.dts28 #size-cells = <0>;
30 PowerPC,8555@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8560.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
[all …]
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dmpc8349emitx.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; // from bootloader
[all …]
H A Dmpc8313erdb.dts26 #size-cells = <0>;
28 PowerPC,8313@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dtqm8548.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
33 nor@0,0 {
37 reg = <0x0 0x0 0x02000000>;
42 bcsr@1,0 {
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Dcn9131-cf-solidwan.dts23 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
24 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
69 pinctrl-0 = <&cp0_led_pins &cp1_led_pins>;
99 pinctrl-0 = <&cp0_reg_usb_a_vbus0_pins>;
111 pinctrl-0 = <&cp0_reg_usb_a_vbus1_pins>;
121 sfp0: sfp-0 {
123 pinctrl-0 = <&cp0_sfp0_pins>;
127 mod-def0-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
135 pinctrl-0 = <&cp1_sfp1_pins>;
154 phys = <&cp0_comphy2 0>;
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi14 bootscr-address = /bits/ 64 <0x3000000>;
20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
54 interrupts = <0 5 4>, <0 6 4>;
56 reg = <0xf8891000 0x1000>,
57 <0xf8893000 0x1000>;
76 #size-cells = <0>;
79 port@0 {
80 reg = <0>;
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x.dtsi27 #size-cells = <0>;
29 cpu@0 {
33 reg = <0x0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
58 #clock-cells = <0>;
68 reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
90 reg = <0x00200000 0x80000>,
91 <0xe0808000 0x400>;
[all …]
/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_main.c17 #define XTR_EOF_0 0x00000080U
18 #define XTR_EOF_1 0x01000080U
19 #define XTR_EOF_2 0x02000080U
20 #define XTR_EOF_3 0x03000080U
21 #define XTR_PRUNED 0x04000080U
22 #define XTR_ABORT 0x05000080U
23 #define XTR_ESCAPE 0x06000080U
24 #define XTR_NOT_READY 0x07000080U
42 { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */
43 { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */
[all …]