Home
last modified time | relevance | path

Searched +full:0 +full:xe1000000 (Results 1 – 25 of 29) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dpl353-smc.txt28 reg = <0xe000e000 0x1000>;
31 ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
32 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
33 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
36 reg = <0 0 0x1000000>;
41 reg = <1 0 0x2000000>;
45 reg = <2 0 0x2000000>;
H A Darm,pl353-smc.yaml29 pattern: "^memory-controller@[0-9a-f]+$"
63 <cs-number> 0 <offset> <size>
65 - description: NAND bank 0
66 - description: NOR/SRAM bank 0
72 "@[0-3],[a-f0-9]+$":
89 minimum: 0
115 reg = <0xe000e000 0x0001000>;
118 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
119 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
120 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
[all …]
H A Darm,pl35x-smc.yaml33 pattern: "^memory-controller@[0-9a-f]+$"
69 - description: Combined or Memory interface 0 IRQ
73 "@[0-7],[a-f0-9]+$":
91 minimum: 0
141 reg = <0xe000e000 0x0001000>;
144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
150 nfc0: nand-controller@0,0 {
152 reg = <0 0 0x1000000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml37 reg = <0xe000e000 0x0001000>;
40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
46 nfc0: nand-controller@0,0 {
48 reg = <0 0 0x1000000>;
50 #size-cells = <0>;
H A Dintel,lgm-ebunand.yaml48 minimum: 0
70 reg = <0xe0f00000 0x100>,
71 <0xe1000000 0x300>,
72 <0xe1400000 0x8000>,
73 <0xe1c00000 0x1000>,
74 <0x17400000 0x4>,
75 <0x17c00000 0x4>;
82 #size-cells = <0>;
84 nand@0 {
85 reg = <0>;
H A Dintel,lgm-nand.yaml46 const: 0
53 minimum: 0
79 reg = <0xe0f00000 0x100>,
80 <0xe1000000 0x300>,
81 <0xe1400000 0x8000>,
82 <0xe1c00000 0x1000>,
83 <0x17400000 0x4>,
84 <0x17c00000 0x4>;
91 #size-cells = <0>;
93 nand@0 {
[all …]
/freebsd/sys/dts/arm/
H A Dannapurna-alpine.dts41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0x0>;
49 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = <0>;
53 clock-frequency = <0>;
59 reg = <0x0>;
62 d-cache-size = <0x8000>; // L1, 32K
63 i-cache-size = <0x8000>; // L1, 32K
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_reg.h38 /* PL AXI buses: General Purpose Port #0, M_AXI_GP0. */
39 #define ZYNQ7_PLGP0_HWBASE 0x40000000
40 #define ZYNQ7_PLGP0_SIZE 0x40000000
43 #define ZYNQ7_PLGP1_HWBASE 0x80000000
44 #define ZYNQ7_PLGP1_SIZE 0x40000000
47 #define ZYNQ7_PSIO_HWBASE 0xE0000000
48 #define ZYNQ7_PSIO_SIZE 0x00300000
52 #define ZYNQ7_UART0_SIZE 0x1000
54 #define ZYNQ7_UART1_HWBASE (ZYNQ7_PSIO_HWBASE+0x1000)
55 #define ZYNQ7_UART1_SIZE 0x1000
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcm6490-shift-otter.dts44 reg = <0x0 0xe1000000 0x0 (2400 * 1080 * 4)>;
56 pinctrl-0 = <&volume_down_default>;
71 #size-cells = <0>;
73 connector@0 {
75 reg = <0>;
81 #size-cells = <0>;
83 port@0 {
84 reg = <0>;
112 reg = <0x0 0xe1000000 0x0 0x2300000>;
117 reg = <0x0 0x88f00000 0x0 0x1e00000>;
[all …]
H A Dsm8350-sony-xperia-sagami.dtsi33 reg = <0 0xe1000000 0 0x2300000>;
53 pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>;
94 reg = <0 0xe1000000 0 0x2300000>;
100 reg = <0 0xffc00000 0 0x100000>;
101 console-size = <0x40000>;
102 record-size = <0x1000>;
124 regulators-0 {
496 reg = <0x40>;
511 reg = <0x41>;
592 power-source = <0>;
[all …]
H A Dqcm6490-fairphone-fp5.dts42 reg = <0x0 0xe1000000 0x0 (2700 * 1224 * 4)>;
54 pinctrl-0 = <&volume_down_default>, <&hall_sensor_default>;
78 #size-cells = <0>;
82 connector@0 {
84 reg = <0>;
90 #size-cells = <0>;
92 port@0 {
93 reg = <0>;
113 reg = <0x0 0xe1000000 0x0 0x2300000>;
118 reg = <0x0 0x88f00000 0x0 0x1e00000>;
[all …]
H A Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 CPU0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
H A Dmpc8610_hpcd.dts26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h50 0x00000001, 0x00000002, 0x00000004, 0x00000008,
51 0x00000010, 0x00000020, 0x00000040, 0x00000080,
52 0x0000001b, 0x00000036
58 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
59 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
60 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
61 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
62 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
63 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
64 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dsama7g5.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
88 hysteresis = <0>;
94 hysteresis = <0>;
100 hysteresis = <0>;
122 #clock-cells = <0>;
127 #clock-cells = <0>;
132 #clock-cells = <0>;
151 reg = <0x100000 0x20000>;
[all …]
/freebsd/sys/dev/sym/
H A Dsym_defs.h67 #define PCI_VENDOR_NCR 0x1000
78 #define PCI_ID_SYM53C875 0xf
79 #define PCI_ID_SYM53C875_2 0x8f
80 #define PCI_ID_SYM53C885 0xd
81 #define PCI_ID_SYM53C895 0xc
82 #define PCI_ID_SYM53C896 0xb
83 #define PCI_ID_SYM53C895A 0x12
84 #define PCI_ID_LSI53C1010 0x20
85 #define PCI_ID_LSI53C1010_2 0x21
86 #define PCI_ID_LSI53C1510D 0xa
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMask.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 0xf0000000,
18 0xb0000000,
19 0x0fe03fe0,
20 0 },
23 0xffc00000,
24 0x76000000,
25 0x00203fe0,
26 0 },
29 0xff800000,
[all …]
/freebsd/sys/dev/bxe/
H A Decore_hsi.h33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
41 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
47 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
49 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
61 #define PIN_CFG_NA 0x00000000
62 #define PIN_CFG_GPIO0_P0 0x00000001
63 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/sys/dev/ispfw/
H A Dasm_2500.h38 0x0501f06b, 0x00115000, 0x00100000, 0x0000c8ea,
39 0x00000008, 0x00000008, 0x000000cf, 0x00109095,
40 0x00000004, 0x00000000, 0x20434f50, 0x59524947,
41 0x48542032, 0x30313920, 0x514c4f47, 0x49432043,
42 0x4f52504f, 0x52415449, 0x4f4e2020, 0x20495350,
43 0x32357878, 0x20466972, 0x6d776172, 0x65202020,
44 0x56657273, 0x696f6e20, 0x2020382e, 0x30382e32,
45 0x30372020, 0x24000000, 0x00000000, 0x00000000,
46 0x00000000, 0x00000000, 0x00100000, 0x00100000,
47 0x0000c8ea, 0xffffffff, 0x00115004, 0x00020000,
[all …]

12