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Searched +full:0 +full:xe1000 (Results 1 – 13 of 13) sorted by relevance

/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dqoriq-clockgen1.dtsi2 * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
37 reg = <0xe1000 0x1000>;
H A Dqoriq-clockgen2.dtsi2 * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
37 reg = <0xe1000 0x1000>;
H A Dqoriq-fman3-0-10g-2.dtsi3 * QorIQ FMan v3 10g port #2 device tree stub [ controller @ offset 0x400000 ]
11 cell-index = <0x8>;
13 reg = <0x88000 0x1000>;
18 cell-index = <0x28>;
20 reg = <0xa8000 0x1000>;
25 cell-index = <0>;
27 reg = <0xe0000 0x1000>;
36 #size-cells = <0>;
38 reg = <0xe1000 0x1000>;
41 pcsphy0: ethernet-phy@0 {
[all …]
H A Dqoriq-fman3-1-1g-0.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
60 #size-cells = <0>;
62 reg = <0xe1000 0x1000>;
65 pcsphy8: ethernet-phy@0 {
[all …]
H A Dqoriq-fman3-0-1g-0.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
43 cell-index = <0x28>;
45 reg = <0xa8000 0x1000>;
49 cell-index = <0>;
51 reg = <0xe0000 0x1000>;
60 #size-cells = <0>;
62 reg = <0xe1000 0x1000>;
65 pcsphy0: ethernet-phy@0 {
[all …]
H A Dqoriq-fman3-0-10g-0-best-effort.dtsi2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x8>;
39 reg = <0x88000 0x1000>;
45 cell-index = <0x28>;
47 reg = <0xa8000 0x1000>;
53 cell-index = <0>;
55 reg = <0xe0000 0x1000>;
64 #size-cells = <0>;
66 reg = <0xe1000 0x1000>;
69 pcsphy0: ethernet-phy@0 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dfsl,qoriq-clock.yaml88 0 sysclk must be 0
91 3 fman 0 for fm1, 1 for fm2
94 5 coreclk must be 0
116 '^mux[0-9]@[a-f0-9]+$':
124 '^pll[0-9]@[a-f0-9]+$':
144 reg = <0xe1000 0x1000>;
153 reg = <0xe1000 0x1000>;
154 ranges = <0x0 0xe1000 0x1000>;
163 #clock-cells = <0>;
168 reg = <0x800 0x4>;
[all …]
H A Dqoriq-clock.txt84 0 sysclk must be 0
87 3 fman 0 for fm1, 1 for fm2
90 5 coreclk must be 0
97 reg = <0xe1000 0x1000>;
103 clocks = <&clockgen 3 0>;
117 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
118 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
119 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
120 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
121 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dqoriq-fman3-0-1g-0.dtsi3 * QorIQ FMan v3 1g port #0 device tree
11 cell-index = <0x8>;
13 reg = <0x88000 0x1000>;
17 cell-index = <0x28>;
19 reg = <0xa8000 0x1000>;
23 cell-index = <0>;
25 reg = <0xe0000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xe1000 0x1000>;
38 pcsphy0: ethernet-phy@0 {
[all …]
/freebsd/sys/dts/powerpc/
H A Dp3041si.dtsi103 #size-cells = <0>;
105 cpu0: PowerPC,e500mc@0 {
107 reg = <0>;
145 dcsr-epu@0 {
147 interrupts = <52 2 0 0
148 84 2 0 0
149 85 2 0 0>;
151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
[all …]
H A Dp2041si.dtsi102 #size-cells = <0>;
104 cpu0: PowerPC,e500mc@0 {
106 reg = <0>;
144 dcsr-epu@0 {
146 interrupts = <52 2 0 0
147 84 2 0 0
148 85 2 0 0>;
150 reg = <0x0 0x1000>;
154 reg = <0x1000 0x1000 0x1000000 0x8000>;
158 reg = <0x2000 0x1000>;
[all …]
H A Dp5020si.dtsi109 #size-cells = <0>;
111 cpu0: PowerPC,e5500@0 {
113 reg = <0>;
135 dcsr-epu@0 {
137 interrupts = <52 2 0 0
138 84 2 0 0
139 85 2 0 0>;
141 reg = <0x0 0x1000>;
145 reg = <0x1000 0x1000 0x1000000 0x8000>;
149 reg = <0x2000 0x1000>;
[all …]
/freebsd/sys/dev/bxe/
H A Dbxe_dump.h33 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
34 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
35 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
36 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
56 #define BNX2X_DUMP_VERSION 0x61111111
76 static const uint32_t page_vals_e2[] = {0, 128};
79 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
85 static const uint32_t page_vals_e3[] = {0, 128};
88 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
92 { 0x2000, 1, 0x1f, 0xfff},
[all …]