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/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,comphy-cp110.yaml32 - description: Lane 0 (USB3/GbE) registers (Armada 3700)
47 const: 0
64 '^phy@[0-2]$':
108 reg = <0x120000 0x6000>;
112 #size-cells = <0>;
115 phy@0 {
116 reg = <0>;
129 reg = <0x18300 0x300>,
130 <0x1F000 0x400>,
131 <0x5C000 0x400>,
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-37xx.dtsi33 reg = <0 0x4000000 0 0x200000>;
38 reg = <0 0x4400000 0 0x1000000>;
45 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
83 /* 32M internal register @ 0xd000_0000 */
84 ranges = <0x0 0x0 0xd0000000 0x2000000>;
88 reg = <0x8300 0x40>;
96 reg = <0xd000 0x1000>;
102 #size-cells = <0>;
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/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dmme1_ctrl_regs.h22 #define mmMME1_CTRL_ARCH_STATUS 0xE0000
24 #define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_S 0xE0008
26 #define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_L 0xE000C
28 #define mmMME1_CTRL_ARCH_BASE_ADDR_HIGH_O 0xE0010
30 #define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_S 0xE0014
32 #define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_L 0xE0018
34 #define mmMME1_CTRL_ARCH_BASE_ADDR_LOW_O 0xE001C
36 #define mmMME1_CTRL_ARCH_HEADER_LOW 0xE0020
38 #define mmMME1_CTRL_ARCH_HEADER_HIGH 0xE0024
40 #define mmMME1_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0xE0028
[all …]