Searched +full:0 +full:xd2010000 (Results 1 – 3 of 3) sorted by relevance
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).46 reg = <0xd1800000 0x1000 /* FSMC Register */47 0xd2000000 0x0010 /* NAND Base DATA */48 0xd2020000 0x0010 /* NAND Base ADDR */49 0xd2010000 0x0010>; /* NAND Base CMD */54 timings = /bits/ 8 <0 0 0 2 3 0>;57 partition@0 {
12 #address-cells = <0>;13 #size-cells = <0>;23 reg = <0 0x40000000>;30 ranges = <0xd0000000 0xd0000000 0x30000000>;35 reg = <0xf1100000 0x1000>;42 reg = <0xf1000000 0x1000>;48 reg = <0xfc200000 0x1000>;56 reg = <0xfc400000 0x1000>;64 reg = <0xe0800000 0x8000>;76 reg = <0xd1800000 0x1000 /* FSMC Register */[all …]
23 #size-cells = <0>;270 reg = <0x10000>;273 numa-node-id = <0>;279 reg = <0x10001>;282 numa-node-id = <0>;288 reg = <0x10002>;291 numa-node-id = <0>;297 reg = <0x10003>;300 numa-node-id = <0>;306 reg = <0x10100>;[all …]