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/linux/drivers/net/ethernet/aquantia/atlantic/
H A Daq_common.h19 #define PCI_VENDOR_ID_AQUANTIA 0x1D6A
21 #define AQ_DEVICE_ID_0001 0x0001
22 #define AQ_DEVICE_ID_D100 0xD100
23 #define AQ_DEVICE_ID_D107 0xD107
24 #define AQ_DEVICE_ID_D108 0xD108
25 #define AQ_DEVICE_ID_D109 0xD109
27 #define AQ_DEVICE_ID_AQC100 0x00B1
28 #define AQ_DEVICE_ID_AQC107 0x07B1
29 #define AQ_DEVICE_ID_AQC108 0x08B1
30 #define AQ_DEVICE_ID_AQC109 0x09B1
[all …]
/linux/drivers/iio/chemical/
H A Dscd30_i2c.c7 * I2C slave address: 0x61
21 #define SCD30_I2C_CRC8_POLYNOMIAL 0x31
24 [CMD_START_MEAS] = 0x0010,
25 [CMD_STOP_MEAS] = 0x0104,
26 [CMD_MEAS_INTERVAL] = 0x4600,
27 [CMD_MEAS_READY] = 0x0202,
28 [CMD_READ_MEAS] = 0x0300,
29 [CMD_ASC] = 0x5306,
30 [CMD_FRC] = 0x5204,
31 [CMD_TEMP_OFFSET] = 0x5403,
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H A Dsps30_i2c.c7 * I2C slave address: 0x69
21 #define SPS30_I2C_CRC8_POLYNOMIAL 0x31
27 #define SPS30_I2C_START_MEAS 0x0010
28 #define SPS30_I2C_STOP_MEAS 0x0104
29 #define SPS30_I2C_READ_MEAS 0x0300
30 #define SPS30_I2C_MEAS_READY 0x0202
31 #define SPS30_I2C_RESET 0xd304
32 #define SPS30_I2C_CLEAN_FAN 0x5607
33 #define SPS30_I2C_PERIOD 0x8004
34 #define SPS30_I2C_READ_SERIAL 0xd033
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/linux/drivers/i2c/busses/
H A Di2c-cp2615.c17 #define CP2615_VID 0x10c4
18 #define CP2615_PID 0xeac1
20 #define IOP_EP_IN 0x82
21 #define IOP_EP_OUT 0x02
30 iop_GetAccessoryInfo = 0xD100,
31 iop_AccessoryInfo = 0xA100,
32 iop_GetPortConfiguration = 0xD203,
33 iop_PortConfiguration = 0xA203,
34 iop_DoI2cTransfer = 0xD400,
35 iop_I2cTransferResult = 0xA400,
[all …]
/linux/drivers/media/usb/gspca/
H A Dstk1135.c51 if (gspca_dev->usb_err < 0) in reg_r()
52 return 0; in reg_r()
53 ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), in reg_r()
54 0x00, in reg_r()
56 0x00, in reg_r()
61 gspca_dbg(gspca_dev, D_USBI, "reg_r 0x%x=0x%02x\n", in reg_r()
62 index, gspca_dev->usb_buf[0]); in reg_r()
63 if (ret < 0) { in reg_r()
64 pr_err("reg_r 0x%x err %d\n", index, ret); in reg_r()
66 return 0; in reg_r()
[all …]
H A Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
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/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dcore-imp-def.json4 "EventCode": "0x10A",
10 "EventCode": "0x10B",
16 "EventCode": "0x110",
22 "EventCode": "0x111",
28 "EventCode": "0x112",
34 "EventCode": "0x113",
40 "EventCode": "0x114",
46 "EventCode": "0x115",
52 "EventCode": "0x116",
58 "EventCode": "0x117",
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/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A Dcore-imp-def.json4 "EventCode": "0x10A",
10 "EventCode": "0x10B",
16 "EventCode": "0x110",
22 "EventCode": "0x111",
28 "EventCode": "0x112",
34 "EventCode": "0x113",
40 "EventCode": "0x114",
46 "EventCode": "0x115",
52 "EventCode": "0x116",
58 "EventCode": "0x117",
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/linux/sound/soc/codecs/
H A Drt1318-sdw.c24 { 0xc001, 0x43 },
25 { 0xc003, 0xa2 },
26 { 0xc004, 0x44 },
27 { 0xc005, 0x44 },
28 { 0xc006, 0x33 },
29 { 0xc007, 0x64 },
30 { 0xc320, 0x20 },
31 { 0xf203, 0x18 },
32 { 0xf211, 0x00 },
33 { 0xf212, 0x26 },
[all …]
H A Drt1320-sdw.c31 { 0xc003, 0xe0 },
32 { 0xc01b, 0xfc },
33 { 0xc5c3, 0xf2 },
34 { 0xc5c2, 0x00 },
35 { 0xc5c6, 0x1
[all...]
/linux/drivers/comedi/drivers/
H A Dadv_pci1710.c41 #define PCI171X_AD_DATA_REG 0x00 /* R: A/D data */
42 #define PCI171X_SOFTTRG_REG 0x00 /* W: soft trigger for A/D */
43 #define PCI171X_RANGE_REG 0x02 /* W: A/D gain/range register */
46 #define PCI171X_RANGE_GAIN(x) (((x) & 0x7) << 0)
47 #define PCI171X_MUX_REG 0x04 /* W: A/D multiplexor control */
48 #define PCI171X_MUX_CHANH(x) (((x) & 0xff) << 8)
49 #define PCI171X_MUX_CHANL(x) (((x) & 0xff) << 0)
51 #define PCI171X_STATUS_REG 0x06 /* R: status register */
56 #define PCI171X_CTRL_REG 0x06 /* W: control register */
57 #define PCI171X_CTRL_CNT0 BIT(6) /* 1=ext. clk, 0=int. 100kHz clk */
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/linux/drivers/scsi/qla2xxx/
H A Dqla_tmpl.c12 #define INVALID_ENTRY ((struct qla27xx_fwdt_entry *)0xffffffffffffffffUL)
47 uint8_t value = ~0; in qla27xx_read8()
58 uint16_t value = ~0; in qla27xx_read16()
69 uint32_t value = ~0; in qla27xx_read32()
139 ql_dbg(ql_dbg_misc, vha, 0xd100, in qla27xx_fwdt_entry_t0()
150 ql_dbg(ql_dbg_misc, vha, 0xd1ff, in qla27xx_fwdt_entry_t255()
167 ql_dbg(ql_dbg_misc, vha, 0xd200, in qla27xx_fwdt_entry_t256()
182 ql_dbg(ql_dbg_misc, vha, 0xd201, in qla27xx_fwdt_entry_t257()
201 ql_dbg(ql_dbg_misc, vha, 0xd202, in qla27xx_fwdt_entry_t258()
219 ql_dbg(ql_dbg_misc, vha, 0xd203, in qla27xx_fwdt_entry_t259()
[all …]
/linux/Documentation/networking/
H A Darcnet-hardware.rst269 values in the Linux ARCnet driver are only from 0x200 through 0x3F0. (If
272 a doc I got from Novell, MS Windows prefers values of 0x300 or more,
274 this may be because, if your card is at 0x2E0, probing for a serial port
275 at 0x2E8 will reset the card and probably mess things up royally.
277 - Avery's favourite: 0x300.
292 IRQ 0 Timer 0 (Not on bus)
340 Anything less than 0xA0000 is, well, a BAD idea since it isn't above
343 - Avery's favourite: 0xD0000
346 address from 0 to 255. Unlike Ethernet, you can set this address
349 on a network. DON'T use 0 or 255, since these are reserved (although
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
H A Dgfx_7_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
H A Dgfx_8_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
H A Dgfx_8_1_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_9_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]
H A Dnbio_4_3_0_offset.h29 // base address: 0x0
30 …BIF_BX0_PCIE_INDEX 0x000c
31 …e regBIF_BX0_PCIE_INDEX_BASE_IDX 0
32 …BIF_BX0_PCIE_DATA 0x000d
33 …e regBIF_BX0_PCIE_DATA_BASE_IDX 0
34 …BIF_BX0_PCIE_INDEX2 0x000e
35 …e regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
36 …BIF_BX0_PCIE_DATA2 0x000f
37 …e regBIF_BX0_PCIE_DATA2_BASE_IDX 0
38 …BIF_BX0_PCIE_INDEX_HI 0x0010
[all …]
H A Dnbio_7_2_0_offset.h26 // base address: 0x0
27 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000
28 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002
29 …BIF_CFG_DEV0_RC_COMMAND 0x0004
30 …BIF_CFG_DEV0_RC_STATUS 0x0006
31 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008
32 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
33 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a
34 …BIF_CFG_DEV0_RC_BASE_CLASS 0x000b
35 …BIF_CFG_DEV0_RC_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_7_0_offset.h29 // base address: 0x0
30 …NBCFG_SCRATCH_4 0x0078
34 // base address: 0x0
35 …BIF_CFG_DEV0_RC_VENDOR_ID 0x0000
36 …BIF_CFG_DEV0_RC_DEVICE_ID 0x0002
37 …BIF_CFG_DEV0_RC_COMMAND 0x0004
38 …BIF_CFG_DEV0_RC_STATUS 0x0006
39 …BIF_CFG_DEV0_RC_REVISION_ID 0x0008
40 …BIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009
41 …BIF_CFG_DEV0_RC_SUB_CLASS 0x000a
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_3_1_offset.h28 // base address: 0x0
29 …IRQ_BRIDGE_CNTL 0x003e
33 // base address: 0x0
34 …BIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000
35 …BIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002
36 …BIF_CFG_DEV0_EPF0_COMMAND 0x0004
37 …BIF_CFG_DEV0_EPF0_STATUS 0x0006
38 …BIF_CFG_DEV0_EPF0_REVISION_ID 0x0008
39 …BIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009
40 …BIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c54 * at the time it indicated completion is stored there. Returns 0 if the
66 return 0; in t4_wait_op_done_val()
68 if (--attempts == 0) in t4_wait_op_done_val()
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()
169 * ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
247 log->cursor = 0; in t4_record_mbox()
249 for (i = 0; i < size / 8; i++) in t4_record_mbox()
252 entry->cmd[i++] = 0; in t4_record_mbox()
277 * The return value is 0 on success or a negative errno on failure. A
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/linux/fs/nls/
H A Dnls_cp949.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x0000,0xAC02,0xAC03,0xAC05,0xAC06,0xAC0B,0xAC0C,0xAC0D,/* 0x40-0x47 */
26 0xAC0E,0xAC0F,0xAC18,0xAC1E,0xAC1F,0xAC21,0xAC22,0xAC23,/* 0x48-0x4F */
[all …]