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/linux/arch/arm/boot/dts/st/
H A Dspear3xx.dtsi14 #address-cells = <0>;
15 #size-cells = <0>;
25 reg = <0 0x40000000>;
32 ranges = <0xd0000000 0xd0000000 0x30000000>;
37 reg = <0xf1100000 0x1000>;
43 reg = <0xfc400000 0x1000>;
51 reg = <0xe0800000 0x8000>;
62 reg = <0xfc000000 0x1000>;
69 reg = <0xd0100000 0x1000>;
72 #size-cells = <0>;
[all …]
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
51 reg = <0x50000000 0x1000>;
[all …]
H A Dspear310.dtsi15 ranges = <0x40000000 0x40000000 0x10000000
16 0xb0000000 0xb0000000 0x10000000
17 0xd0000000 0xd0000000 0x30000000>;
21 reg = <0xb4000000 0x1000>;
29 reg = <0x44000000 0x1000 /* FSMC Register */
30 0x40000000 0x0010 /* NAND Base DATA */
31 0x40020000 0x0010 /* NAND Base ADDR */
32 0x40010000 0x0010>; /* NAND Base CMD */
39 reg = <0xb4000000 0x1000>;
49 ranges = <0xb0000000 0xb0000000 0x10000000
[all …]
H A Dspear320.dtsi15 ranges = <0x40000000 0x40000000 0x80000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0xb3000000 0x1000>;
26 reg = <0x90000000 0x1000>;
36 reg = <0x4c000000 0x1000 /* FSMC Register */
37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
46 reg = <0x70000000 0x100>;
54 reg = <0xb3000000 0x1000>;
[all …]
H A Dspear600.dtsi12 #address-cells = <0>;
13 #size-cells = <0>;
23 reg = <0 0x40000000>;
30 ranges = <0xd0000000 0xd0000000 0x30000000>;
35 reg = <0xf1100000 0x1000>;
42 reg = <0xf1000000 0x1000>;
48 reg = <0xfc200000 0x1000>;
56 reg = <0xfc400000 0x1000>;
64 reg = <0xe0800000 0x8000>;
76 reg = <0xd1800000 0x1000 /* FSMC Register */
[all …]
/linux/arch/arm/configs/
H A Ddram_0xd0000000.config1 # Help: DRAM base at 0xd0000000
2 CONFIG_DRAM_BASE=0xd0000000
/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
H A Dnvidia,tegra20-gmi.txt54 Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
57 bus. Valid values are 0-15, default is 1
60 (in case of MASTER Request). Valid values are 0-15, default is 1
62 Valid values are 0-15, default is 1.
64 Valid values are 0-15, default is 4
66 Valid values are 0-15, default is 1
68 Valid values are 0-255, default is 1
70 Valid values are 0-255, default is 3
78 reg = <0x70009000 0x1000>;
85 ranges = <4 0 0xd0000000 0xfffffff>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dintegratorap.dts17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
/linux/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-crs328-4c-20s-4s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-xp-crs305-1g-4s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-xp-crs326-24g-2s.dtsi11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
33 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
50 devbus,badr-skew-ps = <0>;
53 devbus,rd-setup-ps = <0>;
54 devbus,rd-hold-ps = <0>;
57 devbus,sync-enable = <0>;
83 flash@0 {
87 reg = <0>; /* Chip select 0 */
[all …]
H A Darmada-xp-db-dxbc2.dts10 * internal registers to 0xf1000000 (instead of the default
11 * 0xd0000000). The 0xf1000000 is the default used by the recent,
14 * left internal registers mapped at 0xd0000000. If you are in this
32 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
45 devbus,badr-skew-ps = <0>;
48 devbus,rd-setup-ps = <0>;
49 devbus,rd-hold-ps = <0>;
52 devbus,sync-enable = <0>;
74 nand@0 {
75 reg = <0>;
[all …]
H A Darmada-xp-db-xc3-24g4xg.dts10 * internal registers to 0xf1000000 (instead of the default
11 * 0xd0000000). The 0xf1000000 is the default used by the recent,
14 * left internal registers mapped at 0xd0000000. If you are in this
32 reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
49 devbus,badr-skew-ps = <0>;
52 devbus,rd-setup-ps = <0>;
53 devbus,rd-hold-ps = <0>;
56 devbus,sync-enable = <0>;
78 nand@0 {
79 reg = <0>;
[all …]
H A Darmada-370-synology-ds213j.dts8 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
13 * registers mapped at 0xd0000000. If you have such a device you will
18 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
36 memory@0 {
38 reg = <0x00000000 0x20000000>; /* 512 MB */
42 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
43 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
44 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
55 pinctrl-0 = <&i2c0_pins>;
[all …]
H A Darmada-xp-synology-ds414.dts8 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
13 * registers mapped at 0xd0000000. If you have such a device you will
18 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
36 memory@0 {
38 reg = <0 0x00000000 0 0x40000000>; /* 1GB */
42 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
43 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
44 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
45 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
[all …]
H A Darmada-370-db.dts13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
17 * left internal registers mapped at 0xd0000000. If you are in this
33 memory@0 {
35 reg = <0x00000000 0x40000000>; /* 1 GB */
39 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
40 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
41 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
53 pinctrl-0 = <&ge0_rgmii_pins>;
60 pinctrl-0 = <&ge1_rgmii_pins>;
[all …]
H A Darmada-xp-db.dts14 * internal registers to 0xf1000000 (instead of the default
15 * 0xd0000000). The 0xf1000000 is the default used by the recent,
18 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
36 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
43 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
44 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
[all …]
H A Darmada-xp-gp.dts13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
17 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
41 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
45 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
46 <0x00000001 0x00000000 0x00000001 0x00000000>;
58 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
59 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
60 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
[all …]
H A Darmada-370-rd.dts11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
35 memory@0 {
37 reg = <0x00000000 0x20000000>; /* 512 MB */
41 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
42 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
43 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
60 pinctrl-0 = <&ge1_rgmii_pins>;
71 pinctrl-0 = <&sdio_pins1>;
[all …]
/linux/arch/m68k/include/asm/
H A Dpgtable_mm.h33 } while(0)
76 #define KMAP_START 0x0dc00000
77 #define KMAP_END 0x0e000000
79 #define KMAP_START 0xe0000000
80 #define KMAP_END 0xf0000000
82 #define KMAP_START 0xdf000000
83 #define KMAP_END 0xff000000
85 #define KMAP_START 0xd0000000
86 #define KMAP_END 0xf0000000
91 #define VMALLOC_START 0x0f800000
[all …]
/linux/drivers/of/unittest-data/
H A Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x50000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/linux/arch/arm/mach-sa1100/include/mach/
H A Dmemory.h22 * node 0: 0xc0000000 - 0xc7ffffff
23 * node 1: 0xc8000000 - 0xcfffffff
24 * node 2: 0xd0000000 - 0xd7ffffff
25 * node 3: 0xd8000000 - 0xdfffffff
33 #define FLUSH_BASE_PHYS 0xe0000000
34 #define FLUSH_BASE 0xf5000000
35 #define FLUSH_BASE_MINICACHE 0xf5100000
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]

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