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/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-apf28.dts15 reg = <0x40000000 0x08000000>;
21 pinctrl-0 = <&duart_pins_a>;
27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
30 partition@0 {
32 reg = <0x0 0x300000>;
37 reg = <0x300000 0x80000>;
42 reg = <0x380000 0x80000>;
47 reg = <0x400000 0x80000>;
52 reg = <0x480000 0x80000>;
57 reg = <0x500000 0x800000>;
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-cc108.dts29 memory@0 {
31 reg = <0x0 0x20000000>;
36 #phy-cells = <0>;
41 #phy-cells = <0>;
58 flash@0 { /* 16 MB */
60 reg = <0x0>;
66 partition@0 {
68 reg = <0x0 0x400000>; /* 4MB */
72 reg = <0x400000 0x400000>; /* 4MB */
76 reg = <0x800000 0x400000>; /* 4MB */
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm6115-tlmm.yaml59 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
101 reg = <0x500000 0x400000>,
102 <0x900000 0x400000>,
103 <0xd00000 0x400000>;
110 gpio-ranges = <&tlmm 0 0 114>;
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
40 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
52 cp0_usb3_0_phy: cp0-usb3-0-phy {
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
63 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
75 flash@0 {
77 reg = <0>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-linksys-mamba.dts6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
34 memory@0 {
36 reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64 pinctrl-0 = <&ge0_rgmii_pins>;
69 bm,pool-long = <0>;
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml23 pattern: "^iommu@[0-9a-f]*"
174 minimum: 0
624 reg = <0xba5e0000 0x10000>;
626 interrupts = <0 32 4>,
627 <0 33 4>,
628 <0 34 4>, /* This is the first context interrupt */
629 <0 35 4>,
630 <0 36 4>,
631 <0 37 4>;
635 /* device with two stream IDs, 0 and 7 */
[all …]