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Searched +full:0 +full:xc400 (Results 1 – 25 of 40) sorted by relevance

12

/linux/drivers/dma/ti/
H A Dk3-psil-priv.h25 * 0x4400 and 0xc400) only the src configuration can be present. If no dst
26 * configuration found the code will look for (dst_thread_id & ~0x8000) to find
H A Dk3-psil-am62a.c83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-am62.c73 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
74 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
75 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
76 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
78 PSIL_PDMA_XY_PKT(0x4300),
79 PSIL_PDMA_XY_PKT(0x4301),
80 PSIL_PDMA_XY_PKT(0x4302),
81 PSIL_PDMA_XY_PKT(0x4303),
82 PSIL_PDMA_XY_PKT(0x4304),
83 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
H A Dk3-psil-am62p.c83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/linux/arch/csky/kernel/
H A Djump_label.c10 #define NOP32_HI 0xc400
11 #define NOP32_LO 0x4820
12 #define BSR_LINK 0xe000
19 int ret = 0; in arch_jump_label_transform()
29 insn[0] = BSR_LINK | in arch_jump_label_transform()
30 ((uint16_t)((unsigned long) offset >> 16) & 0x3ff); in arch_jump_label_transform()
31 insn[1] = (uint16_t)((unsigned long) offset & 0xffff); in arch_jump_label_transform()
33 insn[0] = NOP32_HI; in arch_jump_label_transform()
H A Dftrace.c11 #define NOP 0x4000
12 #define NOP32_HI 0xc400
13 #define NOP32_LO 0x4820
14 #define PUSH_LR 0x14d0
15 #define MOVIH_LINK 0xea3a
16 #define ORI_LINK 0xef5a
17 #define JSR_LINK 0xe8fa
18 #define BSR_LINK 0xe000
46 call[0] = nolr ? NOP : PUSH_LR; in make_jbsr()
54 call[4] = callee & 0xffff; in make_jbsr()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Daq100x.c38 AQ_LINK_STAT = 0xe800,
39 AQ_IMASK_PMA = 0xf000,
42 AQ_XAUI_RX_CFG = 0xc400,
43 AQ_XAUI_TX_CFG = 0xe400,
46 AQ_1G_CTRL = 0xc400,
47 AQ_ANEG_STAT = 0xc800,
50 AQ_FW_VERSION = 0x0020,
51 AQ_IFLAG_GLOBAL = 0xfc00,
52 AQ_IMASK_GLOBAL = 0xff00,
74 CH_WARN(phy->adapter, "PHY%d: reset failed (0x%x).\n", in aq100x_reset()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Ddavinci-mcasp-audio.yaml35 description: 0 - I2S or 1 - DIT operation mode
37 - 0
52 0 - Inactive, 1 - TX, 2 - RX
58 minimum: 0
83 0 disables the FIFO use
90 0 disables the FIFO use
97 0 - 3-state, 2 - logic low, 3 - logic high
99 - 0
154 const: 0
175 - 0
[all …]
/linux/drivers/staging/media/meson/vdec/
H A Dhevc_regs.h9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
/linux/drivers/net/dsa/
H A Dbcm_sf2_regs.h13 REG_SWITCH_CNTRL = 0,
36 #define MDIO_MASTER_SEL (1 << 0)
39 #define SF2_REV_MASK 0xffff
41 #define SWITCH_TOP_REV_MASK 0xffff
44 #define PHY_REVISION_MASK 0xffff
47 #define IDDQ_BIAS (1 << 0)
54 #define PHY_PHYAD_MASK 0x1F
57 #define CROSSBAR_BCM4908_INT_P7 0
59 #define CROSSBAR_BCM4908_EXT_SERDES 0
64 #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dinit.c94 mt7601u_wr(dev, MT_USB_DMA_CFG, 0); in mt7601u_reset_csr_bbp()
96 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); in mt7601u_reset_csr_bbp()
142 for (i = 0; i < 16; i++) { in mt76_init_beacon_offsets()
148 for (i = 0; i < 4; i++) in mt76_init_beacon_offsets()
167 mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); in mt7601u_write_mac_initvals()
169 return 0; in mt7601u_write_mac_initvals()
181 for (i = 0; i < N_WCIDS; i++) { in mt7601u_init_wcid_mem()
182 vals[i * 2] = 0xffffffff; in mt7601u_init_wcid_mem()
183 vals[i * 2 + 1] = 0x00ffffff; in mt7601u_init_wcid_mem()
210 for (i = 0; i < N_WCIDS * 2; i++) in mt7601u_init_wcid_attr_mem()
[all …]
/linux/include/linux/mfd/
H A Didt8a340_reg.h3 * Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
10 #define PAGE_ADDR_BASE 0x0000
11 #define PAGE_ADDR 0x00fc
13 #define HW_REVISION 0x8180
14 #define REV_ID 0x007a
16 #define HW_DPLL_0 (0x8a00)
17 #define HW_DPLL_1 (0x8b00)
18 #define HW_DPLL_2 (0x8c00)
19 #define HW_DPLL_3 (0x8d00)
20 #define HW_DPLL_4 (0x8e00)
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm4908.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 cpu-release-addr = <0x0 0xff8>;
40 reg = <0x1>;
42 cpu-release-addr = <0x0 0xff8>;
49 reg = <0x2>;
51 cpu-release-addr = <0x0 0xff8>;
58 reg = <0x3>;
60 cpu-release-addr = <0x0 0xff8>;
[all …]
/linux/sound/hda/codecs/realtek/
H A Drealtek.c15 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in coef_mutex_lock()
16 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PROC_COEF, 0); in coef_mutex_lock()
31 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in __alc_read_coefex_idx()
32 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PROC_COEF, coef_val); in __alc_read_coefex_idx()
63 /* a special bypass for COEF 0; read the cached value at the second time */ in alc_write_coefex_idx()
69 spec->coef0 = alc_read_coef_idx(codec, 0); in __alc_update_coefex_idx()
106 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, in alc_process_coef_fw()
133 snd_hda_codec_write(codec, codec->core.afg, 0, in alc_write_gpio_data()
[all...]
/linux/sound/soc/codecs/
H A Drt1318-sdw.c24 { 0xc001, 0x43 },
25 { 0xc003, 0xa2 },
26 { 0xc004, 0x44 },
27 { 0xc005, 0x44 },
28 { 0xc006, 0x33 },
29 { 0xc007, 0x64 },
30 { 0xc320, 0x20 },
31 { 0xf203, 0x18 },
32 { 0xf211, 0x00 },
33 { 0xf212, 0x26 },
[all …]
H A Drt1320-sdw.c31 { 0xc003, 0xe0 },
32 { 0xc01b, 0xfc },
33 { 0xc5c3, 0xf2 },
34 { 0xc5c2, 0x00 },
35 { 0xc5c6, 0x1
[all...]
/linux/drivers/input/misc/
H A Diqs7222.c25 #define IQS7222_PROD_NUM 0x00
31 #define IQS7222_SYS_STATUS 0x10
34 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
41 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
44 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
46 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
48 #define IQS7222_SYS_SETUP 0xD0
55 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
61 #define IQS7222_EVENT_MASK_PROX BIT(0)
63 #define IQS7222_COMMS_HOLD BIT(0)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
H A Dgfx_7_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_COLOR_CONTROL 0xa202
32 #define mmCB_BLEND0_CONTROL 0xa1e0
33 #define mmCB_BLEND1_CONTROL 0xa1e1
34 #define mmCB_BLEND2_CONTROL 0xa1e2
35 #define mmCB_BLEND3_CONTROL 0xa1e3
36 #define mmCB_BLEND4_CONTROL 0xa1e4
[all …]
H A Dgfx_8_0_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
H A Dgfx_8_1_d.h27 #define mmCB_BLEND_RED 0xa105
28 #define mmCB_BLEND_GREEN 0xa106
29 #define mmCB_BLEND_BLUE 0xa107
30 #define mmCB_BLEND_ALPHA 0xa108
31 #define mmCB_DCC_CONTROL 0xa109
32 #define mmCB_COLOR_CONTROL 0xa202
33 #define mmCB_BLEND0_CONTROL 0xa1e0
34 #define mmCB_BLEND1_CONTROL 0xa1e1
35 #define mmCB_BLEND2_CONTROL 0xa1e2
36 #define mmCB_BLEND3_CONTROL 0xa1e3
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/linux/drivers/media/pci/ngene/
H A Dngene-core.c63 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify)) in event_bh_work()
65 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) in event_bh_work()
79 while (Cur->ngeneBuffer.SR.Flags & 0x80) { in demux_bh_work()
82 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_bh_work()
94 leave fill/empty (0x80) flag alone in demux_bh_work()
103 ~0x40; in demux_bh_work()
115 Cur->ngeneBuffer.SR.Flags &= ~0x40; in demux_bh_work()
124 chan->AudioDTOUpdated = 0; in demux_bh_work()
131 if (Cur->ngeneBuffer.SR.Flags & 0x01) in demux_bh_work()
133 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_bh_work()
[all …]

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