Searched +full:0 +full:xc3000 (Results 1 – 5 of 5) sorted by relevance
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | fsl,fman.yaml | 22 FMan block. The offset is 0xc4 from the beginning of the
23 Frame Processing Manager memory map (0xc3000 from the
38 DEVDISR[1] 1 0
43 DCFG_DEVDISR2[6] 1 0
50 DCFG_CCSR_DEVDISR2[24] 1 0
156 reg = <0x400000 0x100000>;
157 ranges = <0 0x400000 0x100000>;
165 fsl,qman-channel-range = <0x40 0xc>;
167 muram@0 {
169 reg = <0x0 0x28000>;
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| /linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-qcs404.c | 42 .ctl_reg = 0x1000 * id, \
43 .io_reg = 0x1000 * id + 0x4, \
44 .intr_cfg_reg = 0x1000 * id + 0x8, \
45 .intr_status_reg = 0x1000 * id + 0xc, \
46 .intr_target_reg = 0x1000 * id + 0x8, \
49 .pull_bit = 0, \
52 .in_bit = 0, \
54 .intr_enable_bit = 0, \
55 .intr_status_bit = 0, \
70 .io_reg = 0, \
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| /linux/drivers/gpu/drm/msm/registers/display/ |
| H A D | mdp4.xml | 11 <value name="VG1" value="0"/>
21 <value name="MIXER0" value="0"/>
30 LCDC_RGB_INTF, /* 0 */
31 DTV_INTF = LCDC_RGB_INTF, /* 0 */
44 <value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) -->
54 <value name="FRAME_LINEAR" value="0"/>
59 <value name="SCALE_FIR" value="0"/>
66 <bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/>
85 <bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/>
102 <reg32 offset="0x00000" name="VERSION">
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| /linux/drivers/interconnect/qcom/ |
| H A D | sm8650.c | 29 .port_offsets = { 0xc000 },
31 .urg_fwd = 0,
32 .prio_fwd_disable = 0,
47 .port_offsets = { 0xd000 },
49 .urg_fwd = 0,
50 .prio_fwd_disable = 0,
74 .port_offsets = { 0xe000 },
76 .urg_fwd = 0,
77 .prio_fwd_disable = 0,
92 .port_offsets = { 0xf000 },
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| /linux/drivers/clk/qcom/ |
| H A D | gcc-sc8280xp.c | 113 .offset = 0x0,
116 .enable_reg = 0x52028,
117 .enable_mask = BIT(0),
128 { 0x1, 2 },
133 .offset = 0x0,
150 .offset = 0x2000,
153 .enable_reg = 0x52028,
165 .offset = 0x76000,
168 .enable_reg = 0x52028,
180 .offset = 0x1a000,
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