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/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
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/linux/tools/testing/selftests/kvm/s390/
H A Dresets.c28 unsigned long cr2_59 = 0x10; /* enable guarded storage */ in guest_code_initial()
29 unsigned long cr8_63 = 0x1; /* monitor mask = 1 */ in guest_code_initial()
36 " lghi 2,0x11\n" /* Round toward 0 */ in guest_code_initial()
37 " sfpc 2\n" /* set fpc to !=0 */ in guest_code_initial()
38 " lctlg 2,2,%0\n" in guest_code_initial()
43 " llihh 0,0xffff\n" in guest_code_initial()
44 " llihl 1,0x5555\n" in guest_code_initial()
45 " llilh 2,0xaaaa\n" in guest_code_initial()
46 " llill 3,0x0000\n" in guest_code_initial()
48 " lghi 4,0x1\n" in guest_code_initial()
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/linux/arch/arm/boot/dts/arm/
H A Dintegratorap-im-pd1.dts21 reg = <0xc2000000 0x00100000>;
28 syscon@0 {
30 reg = <0x00000000 0x1000>;
35 vco1: clock-controller@0 {
37 reg = <0x00 0x04>;
38 #clock-cells = <0>;
39 lock-offset = <0x08>;
40 vco-offset = <0x00>;
47 reg = <0x04 0x04>;
48 #clock-cells = <0>;
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/linux/sound/hda/codecs/
H A Dca0132.c38 #define FLOAT_ZERO 0x00000000
39 #define FLOAT_ONE 0x3f800000
40 #define FLOAT_TWO 0x40000000
41 #define FLOAT_THREE 0x40400000
42 #define FLOAT_FIVE 0x40a00000
43 #define FLOAT_SIX 0x40c00000
44 #define FLOAT_EIGHT 0x41000000
45 #define FLOAT_MINUS_5 0xc0a00000
47 #define UNSOL_TAG_DSP 0x16
56 #define MASTERCONTROL 0x8
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/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c71 #define BAR_0 0
105 #define RESET_KIND_SHUTDOWN 0
109 #define TG3_DEF_RX_MODE 0
110 #define TG3_DEF_TX_MODE 0
195 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
201 #if (NET_IP_ALIGN != 0)
234 module_param(tg3_debug, int, 0);
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
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