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/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
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H A Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
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/linux/arch/arm/boot/dts/arm/
H A Dintegratorap-im-pd1.dts21 reg = <0xc2000000 0x00100000>;
28 syscon@0 {
30 reg = <0x00000000 0x1000>;
35 vco1: clock-controller@0 {
37 reg = <0x00 0x04>;
38 #clock-cells = <0>;
39 lock-offset = <0x08>;
40 vco-offset = <0x00>;
47 reg = <0x04 0x04>;
48 #clock-cells = <0>;
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
H A Dimx95.dtsi24 #size-cells = <0>;
31 arm,psci-suspend-param = <0x0010033>;
40 A55_0: cpu@0 {
43 reg = <0x0>;
61 reg = <0x100>;
79 reg = <0x200>;
97 reg = <0x300>;
115 reg = <0x400>;
133 reg = <0x500>;
248 #clock-cells = <0>;
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/linux/include/linux/firmware/
H A Dxlnx-zynqmp.h21 #define ZYNQMP_PM_VERSION_MINOR 0
27 #define ZYNQMP_TZ_VERSION_MINOR 0
33 #define PM_SIP_SVC 0xC2000000
36 #define GET_SIP_SVC_VERSION (0x8200ff03U)
39 #define SIP_SVC_VERSION_MAJOR (0U)
46 #define PASS_THROUGH_FW_CMD_ID GENMASK(11, 0)
54 #define ZYNQMP_FAMILY_CODE 0x23
55 #define VERSAL_FAMILY_CODE 0x26
58 #define ALL_SUB_FAMILY_CODE 0x00
59 #define VERSAL_SUB_FAMILY_CODE 0x01
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
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/linux/arch/powerpc/
H A DKconfig289 …-flag) -mstack-protector-guard=tls -mstack-protector-guard-reg=r2 -mstack-protector-guard-offset=0)
290 …flag) -mstack-protector-guard=tls -mstack-protector-guard-reg=r13 -mstack-protector-guard-offset=0)
469 default 0
807 default 0x5deadbeef0000000 if PPC64
808 default 0
866 definition from 0x10000 to 0x40000 in older versions.
1192 default "0x30000000"
1244 default "0xc0000000"
1260 default "0xc2000000" if CRASH_DUMP && !NONSTATIC_KERNEL
1261 default "0xc0000000"
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/linux/sound/pci/mixart/
H A Dmixart_mixer.c24 0xc2c00000, /* [000] -96.0 dB */
25 0xc2bf0000, /* [001] -95.5 dB */
26 0xc2be0000, /* [002] -95.0 dB */
27 0xc2bd0000, /* [003] -94.5 dB */
28 0xc2bc0000, /* [004] -94.0 dB */
29 0xc2bb0000, /* [005] -93.5 dB */
30 0xc2ba0000, /* [006] -93.0 dB */
31 0xc2b90000, /* [007] -92.5 dB */
32 0xc2b80000, /* [008] -92.0 dB */
33 0xc2b7000
[all...]
/linux/sound/hda/codecs/
H A Dca0132.c37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
55 #define MASTERCONTROL 0x8
[all...]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c71 #define BAR_0 0
105 #define RESET_KIND_SHUTDOWN 0
109 #define TG3_DEF_RX_MODE 0
110 #define TG3_DEF_TX_MODE 0
195 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
201 #if (NET_IP_ALIGN != 0)
234 module_param(tg3_debug, int, 0);
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
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